8/19/04ELEC / ELEC / Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Fall 2004 Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

8/19/04ELEC / Course Objective Low-power design and self-test are two of the current needs in VLSI design. Learn basic concepts Gain hands-on experience in one of both areas.

8/19/04ELEC / Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. General topics –High-level and software techniques –Gate and circuit-level methods –Power estimation techniques –Test power

8/19/04ELEC / VLSI Chip Power Density Pentium® P Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

8/19/04ELEC / Specific Topics on Low-Power Power dissipation in CMOS circuits Low-power CMOS technologies Dynamic reduction techniques Leakage power Power estimation

8/19/04ELEC / Built-In Self-Test (BIST) Circuit includes hardware to test itself Learn basic concepts of digital BIST Project emphasis on mixed-signal BIST

8/19/04ELEC / Power in a CMOS Gate V DD i DD (t) Ground

8/19/04ELEC / Power and Energy Instantaneous power (Watts) P(t) = i DD (t) V DD Peak power (Watts) P peak = Max {P(t)} Average power (Watts) P av = [ ∫ 0 T P(t) dt ]/T Energy (Joules) E = ∫ 0 T P(t) dt

8/19/04ELEC / Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage

8/19/04ELEC / Power of a Transition V DD Ground C R R Power = CV DD 2 /2

8/19/04ELEC / Logic Activity and Glitches d=2 d=1

8/19/04ELEC / Power Estimation Methods Spice: Accurate but expensive Logic-level –Event-driven simulation –Statistical –Probabilistic High-level: Hierarchical

8/19/04ELEC / Low-Power Design Techniques Circuit design methods – Reduced supply voltage – Adiabatic switching and charge recovery – Logic design for reduced activity – Reduced Glitches – Transistor sizing – Pass-transistor logic – Pseudo-nMOS logic – Multi-threshold gates

8/19/04ELEC / Low-Power Design Techniques Functional and architectural methods –Clock suppression –Power down –Algorithmic and Software methods

8/19/04ELEC / Student Evalulation Homework (30%) – three Student presentation (10%) Research paper (30-60%) – a publishable paper will exempt the student from the final exam Final Exam (0-30%)