Paulo MoreiraInverter1 The CMOS inverter. Paulo MoreiraInverter2 The CMOS inverter.

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Presentation transcript:

Paulo MoreiraInverter1 The CMOS inverter

Paulo MoreiraInverter2 The CMOS inverter

Regions of operation (balanced inverter): V in n-MOSp-MOSV out 0cut-offlinearV dd V TN <V in <V dd /2saturationlinear~V dd V dd /2saturationsaturation V dd /2 V dd -|V TP |>V in >V dd /2linearsaturation~0 V dd linearcut-off0

Paulo MoreiraInverter4 The CMOS inverter C L =250fF

The CMOS inverter Propagation delay Main origin: load capacitance To reduce the delay: Reduce C L Increase k n and k p. That is, increase W/L

Paulo MoreiraInverter6 The CMOS inverter CMOS power budget: –Dynamic power consumption: Charging and discharging of capacitors –Short circuit currents: Short circuit path between power rails during switching –Leakage Leaking diodes and transistors

Paulo MoreiraInverter7 The CMOS inverter The dynamic power dissipation is a function of: –Frequency –Capacitive loading –Voltage swing To reduce dynamic power dissipation –Reduce: C L –Reduce: f –Reduce: V dd  The most effective action

The CMOS inverter

n-well n-well contact (n+) p+ diffusions polysilicon n+ diffusions substrate contact (p+) polysilicon contacts diffusion contactsn-well n-well contact (n+) p+ diffusions polysilicon n+ diffusions substrate contact (p+) polysilicon contacts diffusion contacts

Why The CMOS inverter is Better?? 1) Low DC Power Consumption 2) Abrupt & well defined Voltage transfer Characteristic 3) Noise Immunity due to Low impedance between logic levels and Supply/Gnd. Symmetry between Tfall &Trise. High Density: Si real estate=>Yield=>Cost! Highly Integrated=>Active & High input Impedance=> Composition equality. No real trade off between 1,2,3,4,5 & 6