ANITA RF Conditioning and Digitizing Gary S. Varner University of Hawai, i, Manoa ANITA Collaboration Meeting UC, Irvine 24,25 November 2002

Gary S. Varner, ANITA Collaboration UC Irvine, November Topics RF Signals –Noise Limited RF Electronics –Optimum SNR –Triggering –HS Transient Digitizers Prototypes –STRAW2 –DRS –Advanced ATWD R&D Plans (for discussion)

Gary S. Varner, ANITA Collaboration UC Irvine, November Askaryan Signature Significant signal power at large frequencies Strong linear polarization (near 100%)

Gary S. Varner, ANITA Collaboration UC Irvine, November Single Point Measurement Maximize R for better pointing… trigger latency R Empirically determined Decoherence Freq. Material, aperture Squeeze all possible info.

Gary S. Varner, ANITA Collaboration UC Irvine, November RF Transient Recorder Specs  >= 1GHz analog input bandwidth ( MHz)  multi-GSa/s sampling rate (Nyquist limit ideal)  minimum phase distortion for clean polarization  maximum dynamic range (>= 9 bits)  internal Analog to Digital Conversion (ADC)  short record length ( ns if optimally matched)  self-triggering with fine threshold adjustment  bi-polar triggering  deadtimeless  conclude multi-hit buffering needed

Gary S. Varner, ANITA Collaboration UC Irvine, November Proposed Signal Flow LNA Gain Digitize Trigger [GHz]

Gary S. Varner, ANITA Collaboration UC Irvine, November Straw-man Instrumentation Trigger /Digitizers

Gary S. Varner, ANITA Collaboration UC Irvine, November In principle, can do brute force with off-the-shelf ADCs/backend processing (POWER! But other issues) A number of SCA designs: –DSC (samples obtained, to be tested) –KEK AMC –STRAW2 (SalSa prototype) –Advanced ATWD (Kleinfelder [UCI]) Space/Balloon Transient RF specific: –>1GHz analog input bandwidth –Self-triggering –Low power Possibilities

Gary S. Varner, ANITA Collaboration UC Irvine, November High-speed Digitizers DRC/ DRS close Analog BW not eval.

Gary S. Varner, ANITA Collaboration UC Irvine, November Domino Ring Sampler (DRS) input Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution 1024 bins  150ns waveform + 350ns delay Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution 1024 bins  150ns waveform + 350ns delay Information courtesy of Stefan Ritt (PSI): For further info.: If can keep the sampling jitter small enough (or can measure), no need for a TDC! Switched Capacitor Array (SCA)

Gary S. Varner, ANITA Collaboration UC Irvine, November  Domino Sampling Chip C. Brönnimann et al., NIM A420 (1999) 264 Existing: 0.5 – 1.2 GHz sampling speed 128 sampling cells Readout at 5 MHz, 12 bit ~ 60 $/channel Needed: 2.5 GHz sampling speed Circular domino wave 1024 sampling cells 40 MHz readout Existing: 0.5 – 1.2 GHz sampling speed 128 sampling cells Readout at 5 MHz, 12 bit ~ 60 $/channel Needed: 2.5 GHz sampling speed Circular domino wave 1024 sampling cells 40 MHz readout

Gary S. Varner, ANITA Collaboration UC Irvine, November STRAW2 Specifications Unique in this design is the triggering requirements –High freq and bipolar Large latency strategy: –Multiple buffering

Gary S. Varner, ANITA Collaboration UC Irvine, November STRAW2 Architecture 0.25  m TSMC process

Gary S. Varner, ANITA Collaboration UC Irvine, November Ring Oscillator in 0.25  m CMOS

Gary S. Varner, ANITA Collaboration UC Irvine, November Analog Input Bandwidth! Many examples of high sampling rate, but: –PMT readout –Wireless (2.5GHz) –Very narrow BW –Naïve calculation  phase inductance –3-D Simulation PCB, Package, bond wires BGA necessary? What is fundamental limit ComponentLength/areaUnitFactorFunit Total [fF] Input traces5cm0.2pF/cm1000w.a.g. bonding wire150mil0.3pF/wire300w.a.g. input pad60um^2187fF/pad187Tanner input protection pF/ckt1100SPICE stripline area2500um^243 aF/um^ MOSIS stripline fringe5mm60aF/um300MOSIS Switch Drains256switches5.6fF/drain1433.6SPICE Open Switches6open87fF/gate522SPICE TOTAL pF

Gary S. Varner, ANITA Collaboration UC Irvine, November RF Coupling Simulation die on-chip 50  stripline Utilizes the LC program (FTDT algorithm) –Cray developed, available for free under Linux Bonding wires

Gary S. Varner, ANITA Collaboration UC Irvine, November S-Parameters VSWR: 1.8 [1GHz] 1.9 [2GHz]

Gary S. Varner, ANITA Collaboration UC Irvine, November Logging Performance

Gary S. Varner, ANITA Collaboration UC Irvine, November Self-Triggering

Gary S. Varner, ANITA Collaboration UC Irvine, November Simulation Results Use simulated high freq. Response from beamtest data: –works

Gary S. Varner, ANITA Collaboration UC Irvine, November STRAW2 Chip Submitted for Fab.: 4 Nov. 16 Channels of 256 deep SCA buckets Self-Triggered Recorder Analog Waveform (STRAW) Optimized for RF input Microstrip 50  Record length: ns Self-Triggering: Target input Bandwidth: >700MHz -LL and HL (adj.) for each channel Sampling Rate: 1-2GSa/s (adj.) -Multiplicity trigger for LL hits On-chip ADC: 12-bit, >2MSPS External option: MUXed Analog out Sampling Rates >~8GSa/s possible w/ 0.25  m process 8192 analog storage cells Die:~2.5mm 2

Gary S. Varner, ANITA Collaboration UC Irvine, November Cosmic-ray Radio Testbed Stage 2: Replace TDM with STRAW2 –~200 total antenna signals – get rid of delay cables

Gary S. Varner, ANITA Collaboration UC Irvine, November Evaluation Trigger /Digitizers

Gary S. Varner, ANITA Collaboration UC Irvine, November Readout Board/RF prototype Strong disincentive to purse a “full card” development to start with 10k$ parts!

Gary S. Varner, ANITA Collaboration UC Irvine, November Details…documentation Push to document these details

Gary S. Varner, ANITA Collaboration UC Irvine, November R&D into critical (non-standard) components: –Strong need in other (e.g. precision timing) applications –Not needed for self-triggering/high analog BW (PMTs) –Emphasis on low-power Plans: –STRAW2 Testing (packaged parts ship 12/19) –ANITA evaluation board/backup ADCs –Adv. ATWD Prototype (common START ready for fab.) Discussion: (see next slide) Preliminary Summary

Gary S. Varner, ANITA Collaboration UC Irvine, November Time scale for custom component development –STRAW2 appropriate triggering architecture? Really need trigger waveform recording? –Sample depth/rate and bandwidth for ATWD? –Multi-buffering scheme acceptable? –Still consider RF down-conversion/comm. ADCs? Many disadvantages (large BW DCV, power) Viable fallback? Plans: –STRAW2 Testing (packaged parts ship 12/19) –ANITA evaluation board/backup ADCs –Adv. ATWD Prototype (proto. Waiting for $$) Discussion Items

Gary S. Varner, ANITA Collaboration UC Irvine, November Designs Similar 16 cells All paracitics included Domino speed: GHz 16 cells All paracitics included Domino speed: GHz 10 GHz? TSMC 0.25  m AMC:

Gary S. Varner, ANITA Collaboration UC Irvine, November KEK AMC Analog Memory Cell (AMC) –Common platform –Original AMC follow-on –Super Belle and JHF 0.5  m: LSB ~200ps 0.35  m: LSB ~100ps?