IC Interconnect Modeling Dr. Paul Van Halen PROBLEM  Resistive, capacitive and inductive effects in circuit interconnect impose constraints on mixed- signal system performance.  RLC effects in the interconnect cause signal coupling and result in signal integrity degradation.  Increasing transistor frequency response can result in “in-band” resonant frequencies due to LC interconnect parasitics, which in turn can produce undesirable underdamped behavior (ringing) and system instability (oscillations).  Resistive effects cause ohmic drops in the interconnect which can affect system accuracy and performance.  Resistive effects also can lead to electro- migration and premature field failure. GOAL  Provide circuit designers with accurate RLC extraction, modeling and simulation tools, enabling them to mitigate the impact of interconnect on circuit performance. CHALLENGES  Tools currently available lack accuracy, performance. There is no common user interface and the absence of a common data format necessitates the use of cumbersome “glue” scripts. Professor Van Halen’s research interests are in the general areas of device physics, modeling and characterization and how the models impact the design and simulation of analog ICs. More recently our interests have shifted towards system level modeling and simulation. This shift has been driven by the growing interest in convergence product mixed-signal ASICs, where analog interface circuitry is integrated with high- speed digital signal processing and control systems in the same IC. Mixed-signal ASICs are now the fastest growing market segment in most electronic areas. Personal Communications Systems are but one of a series of new products which signal a convergence of technologies and disciplines: communications, computing and audio and video signal processing. Complex high speed mixed mode systems need a fast and flexible evaluation of concepts and feasibility. Taking advantage of the flexibility and expandability of Tektronix Analog Design System simulation platform, circuit simulation, and measurement. The group of Prof. Van Halen is currently working on functional simulation models of nonlinear dynamic systems: phase-locked loops, Sigma-Delta and other digital modulation schemes. These functional models are characterized through parameter extraction from transistor level simulation and data acquired from measurements, and interfaces with traditional transistor models in critical areas, allow for accurate and fast system simulation of large mixed mode systems. Selected Publications A. Sunardi, G. Boyle, B. Biehl, P. Van Halen, "A Novel Approach for Evaluating Electromigration Effects in Large Analog Integrated Circuits or Reducing the Field Failure Rate of IC's," Tektronix Symposium, A. Sunardi, G. Boyle, B. Biehl, P. Van Halen, "A Novel Approach for Evaluating Electromigration Effects in Large Analog Integrated Circuits or Reducing the Field Failure Rate of IC's," Tektronix Symposium, B. Willoughby, Y. Fu, P. Van Halen, "Design of a Behavioral, SPICE-Compatible Charge-Pump Phase Detector Simulation Model," IEEE Transactions on Circuits and Systems, B. Willoughby, Y. Fu, P. Van Halen, "Design of a Behavioral, SPICE-Compatible Charge-Pump Phase Detector Simulation Model," IEEE Transactions on Circuits and Systems, P. Van Halen, G. Boyle, "A Noise Source for Transient Nonlinear System Simulation," IEEE Transactions on Circuits and Systems, P. Van Halen, G. Boyle, "A Noise Source for Transient Nonlinear System Simulation," IEEE Transactions on Circuits and Systems, P. Van Halen, "Automated Modeling of Interconnect Properties for Current and Future IC Tool Development for ASIC Designs," Tektronix Technical Report, 2003.P. Van Halen, "Automated Modeling of Interconnect Properties for Current and Future IC Tool Development for ASIC Designs," Tektronix Technical Report, P. Van Halen, "Development of an Interconnect Centric Backplane Data Format and API for High Speed ASIC Designs," Tektronix Technical Report, P. Van Halen, "Development of an Interconnect Centric Backplane Data Format and API for High Speed ASIC Designs," Tektronix Technical Report,  Data management: the amount of data is huge. Typically a circuit with fewer than 100,000 transistors will produce an equivalent resistive interconnect network with 5,000,000 to 10,000,000 resistors.  To gauge the impact of the interconnect parasitics we need to be able to simulate these very large systems.  Use hierarchical or windowing techniques to extract parasitic information. STATUS  Use open source tools to provide a common user interface and data management  PostgresQL database for interconnect data and simulation results.  Eclipse for development and deployment of an integrated user interface.  In cooperation with Tektronix (sabbatical ), tools for the management and visualization of ohmic drop and electro-migration effect in ICs were developed.  Figures show how circuit bias, layout information and parasitic extraction data are used to simulate and visualize the ohmic drops in one of the voltage supply nets of an integrated circuit.