06-Dec-2004 HCAL TriDAS 1 TriDAS Status HCAL Group

06-Dec-2004 HCAL TriDAS 2 HTR Status Goal: produce 270 Rev 4.3/4.4 HTRs by end of Summer 05 Current status: –PCB manufacture complete – boards are now at the assembler –Assembler New vendor from Rev 3 version So far boards look good, but some rework needed –Vendor employs optical pattern recognition technology, needed some tuning Assembler agreed to make HTRs in batches of 20 (or larger) –First batch for more tuning, then produce as many as we can handle »~1/week batch of 20, ramping up to batches of later as things get smoother –Parts All parts in hand except octopus (fiber breakouts) – PO went out last Friday –Schedule First batch of HTRs expected end of March –Assembler was told to produce “sandwich” boards first…. Expect to have all HTRs produced, tested, and shipped by ~July

06-Dec-2004 HCAL TriDAS 3 TPG Generation TPG firmware has been well simulated for over 1 year 150 GeV pion beam in HE TPG test performed during synchronous running in Sept 2004 –Trivial identity LUTs for linearization –Form TPGs using simple peak algorithm –Readout with raw data with corresponding TPG –Compare in time

06-Dec-2004 HCAL TriDAS 4 Trigger Primitive Generation

06-Dec-2004 HCAL TriDAS 5 Loading TPG Tables LUT evolution –For actual running – LUTs will be complicated tables Muon bits Pedestal subtraction Calibration sin  A project is underway with the CMS HCAL/EMu/Pixel DB group to store and access the LUT tables from Oracle/MySQL directly into the HTRManager DAQ application. –First production version to be used in SX5, ready for Slice Test Prototype is functional now…

06-Dec-2004 HCAL TriDAS 6 TPG LUT Verification How do we verify the TPG LUT? –We need to know the Xilinx FW and all the TPGs. –Too much data to store all to a central place for verification Solution: store “CRC”s Firmware CRC –HTR uses Altera FPGA for VME and Xilinx FPGA downloading –Each Xilinx download generates 24-bit CRC which is stored for VME readout TPG LUTs –These are smaller, can be easily covered by standard 16-bit CRC –Need an interface between DAQ components and TriDAS stuff to verify CRCs TBD

06-Dec-2004 HCAL TriDAS 7 HTR Firmware Firmware changes for latency –Asynchronous fifo changes from incoming clock phase to common –Will monitor fifo latency and report over VME and to DCC –Reset of fifo over VME –Will also reset fifo after loss-of-link recover (via FSM) Implemented data injection via VME into RAM –Will be useful for Level 1/HTR integration tests Starting to work on zero suppression Not yet working on the variety of summing for TPGs –HB vs HB/HE overlap vs HF Histogram firmware for HCAL sourcing in progress –Need to port to latest HTR revision... this month… Battle tests – will be among many things tested in slice 05

06-Dec-2004 HCAL TriDAS 8 L1 Synchronization Sources of variable latency: –Each TTCrx has variable latency ~20ns Varies chip-to-chip, voltage and temp dependent –TLK2501 has variable latency 76 <  T < 107 bit times, 3 <  T < 6 frames (20bit 80MHz) Plan to track this: –HCAL Front-end tools Fast laser calibration pulses TTC BC0 sent to FE, encoded into data stream –HTR tools SLB histograms Beam in only 1 bucket at some time would be good –Verification…

06-Dec-2004 HCAL TriDAS 9 HTR Production Working on software now Will use separate VME crate/DAQ setup to keep development crate free HTRs will be labeled, tested, cataloged, sent to CERN Will test at Maryland: –Basic operation (FPGA, Localbus, VME) –SLB connectivity Will not test quality of clocking… – BER optical test on all channels Will use RBX if it arrives…otherwise will use emulator

06-Dec-2004 HCAL TriDAS 10 Activities in 904 Test each HTR –Populate each card with 6 SLBs –Test with RCT receiver board –Validate clock, synchronization, quality… Populate VME crates with HTRs and store until November –Will have to wait for the SLBs –Current status has SLBs arriving en masse ~May? System testing, integration, commissioning… –We should push hard on SLB/RCT testing so that SLB firmware settles

06-Dec-2004 HCAL TriDAS 11 HTR SLB Testing Maryland “sandwich” board –HTR and RCT Receiver are the “bread” Used to host RCT receiver to be able to test each link Status: –Prototype validated with RCT Receivers, no problems seen –New version being produced now, ready this week HTR “Sandwich” SLB UW Receiver SLB connector UW receiver connector TOP BOT

06-Dec-2004 HCAL TriDAS 12 Fanout Card Built by Jeremy Mans and Chris Princeton To be used for both ECAL and HCAL to implement synchronization –RX_CLK and RX_BC0 for SLBs

06-Dec-2004 HCAL TriDAS 13 TPG alignment – BCID implementation Unique board for HCAL and possibly ECAL HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR … … Rack-to-Rack CAT 7 Low-skew distribution tree for global BC0 (and CLK) VME : get histograms results and adjust timing Fanout Card (in GLOBAL mode) Fanout Card (in CRATE mode) Fanout Card (in CRATE mode) Fanout Card (in CRATE mode) One board per crate

06-Dec-2004 HCAL TriDAS 14 RX_CLK and RX_BC0 Path TTC fiber CLK40_Des1 FPGA RX_CLK, RX_BC0 TTCrx QPLL FPGA TTCrx QPLL Fanout board in Crate-mode Fanout board in Global-mode 3.3V CMOS Path is 3.3V differential PECL on Cat6 quad twisted pair RX_BC0 is generated from the FPGA decode of TTC broadcast HTR SLB Max skew on HTR traces is 0.7 ns. Spec is: Skew <  12 ns across HCAL and ECAL RX_CLK RX_BC0 TTC and CLK80 added Cat6

06-Dec-2004 HCAL TriDAS 15 Fanout Status All PCBs for non-QPLL “fix” produced but not assembled All parts in hand Waiting a to see how the QPLL issues settle out –Anyone already implemented this, we would appreciate feedback Baseline plan: –Layout with QPLL fix complete and 30 boards submitted –Will assemble 2, available by mid April for testing –If ok, then assemble the rest If not, then assemble the non-QPLL fix version Reminder: This will be used for both ECAL and HCAL