Loran-C Receiver Team Deathstar September 7, 2004 Capstone Fall 2004

Group Members Matt Anderson (ECE) Chris Birschbach (ECE) Christy Corner (EE) Matt Hayman (EE) Erin Mowbray (ECE)

Background: What is Loran-C? Loran-C is a navigation system that was developed by the US Coast Guard. The system is comprised of transmission stations located around the world. The Loran-C signal is transmitted from these stations at specified intervals. By measuring the time delay between transmissions a user can determine their position relative to the towers.

Loran-C Signal

Loran-C Signal continued The Loran-C signal is transmitted on a 100kHz carrier.

Project Purpose Our group will design a receiver that will be able to capture and decode the Loran- C signal maintained by the United States Coast Guard. Our system will consist of three main parts: the antenna/receiver, processing unit and personal computer.

Project Funding Undergraduate Research Opportunities Program (UROP) Grant. Amount: $1750

Tentative Budget ItemDescriptionEstimated Price ProcessorMC68HC912B32 assembled$ LCD Display $75.00 Additional memory $50.00 A to D converter $50.00 Antenna Assembly $ Receiver Enclosure $ Printed Circuit Board $ FPGAXilinx FPGA Evaluation Kit$ Filters 3 Butterworth (8th order)$75.00 RS-232 Interface $25.00 Support ElectronicsResistors, Caps, switches, sockets, cables$ Power Supply $ Student Designed User ManualWeighted Paper, Binding, Printing Costs$ Final Project DisplayPrinted Poster for Engineering Expo$ Loran C User Handbook $25.00 Misc. (Ink Cartridges, Repair parts, Unforeseen Parts needed, additional reference manuals)$ TOTAL:$1,750.00

Project Objectives Capture a clean copy of the Loran-C signal Determine Time Delays Convert to a Latitudinal & Longitudinal coordinates.

Outline of Approach The system will consist of the following subsystems:  Antenna Receiver  Analog-to-digital converter  Motorola 68K processor  Memory  FPGA  Serial Interface  PC  Power

Subsystems Diagram Antenna/ Receiver FPGAPC RAM A/D Converter Processing Unit Processor

Antenna Receiver Subsystem The antenna/receiver will consist of a loop antenna with a active Butterworth filter to capture and amplify the fundamental signal received by the antenna. This segment of the project serves the main purpose of capturing the Loran-C signal with minimal noise and preparing it for processing.

Analog-to-Digital Converter Subsystem The A/D converter will sample the analog signal. Sampling rate will be 1MHz. The digital data will be sent to the FPGA.

FPGA Subsystem The FPGA has a state machine for detecting the third zero crossing of the Loran-C signal. (Generates an interrupt) It functions as a counter to measure the delay between pulses. It includes an interrupt controller for the processor.

Processor Subsystem Upon generation of an interrupt, the processor stores the counter data from the FPGA into RAM. Performs operations on the counter data to determine time delays and stores the delays in RAM. The microcontroller sends the time delay data to the serial interface with the PC.

RAM Subsystem Holds the time delay and counter data for processing and transmission.

Serial Interface Subsystem The communication interface between the PC and the processor. Consists of a serial shift register & RS-232 logic level converter.

PC Subsystem Displays the time delays. Performs intensive conversion calculations to convert data into Latitudinal and Longitudinal coordinates. Displays the Latitudinal and Longitudinal coordinates.

Power Transform, rectify, and regulate voltage from standard 120V/60Hz outlet to required DC voltages. (Or purchase power supply) Include portable power sources (battery or car adapter) if time permits

Tasks Antenna Design Filtering PCB design Memory interface FPGA design PC programming PC interface A/D interface Processor programming Power Users Manual

Schedule

Division of Labor Matt A  Power  Memory interface  Microprocessor Programming Chris B  PC programming  Microprocessor programming  User’s Manual Christy C  Antenna/Filtering  Verilog Design  User’s Manual Matt H  Antenna/Filtering  PCB  Microprocessor Programming  PC programming Erin M  Verilog Design  User’s Manual  PC interface

Risks and Backup Receiving a clean copy of the signal (Can generate a fake signal) Baud rate generation for PC/processor communication  Buffer overflow (Sample slower) Size and complexity of the state machine. (Can shift tasks from the FPGA to the processor to compensate.) RS-232 Communication on PC (Manually entering data into the conversion program)

Above and Beyond If time permits we shall include a LCD display on our receiver that displays the Loran-C time delays. Portable power sources. Cup Holders

Questions and Comments