CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 1 Ch3. Combinatorial Logic Design Modern digital design involves a number of techniques and tools essential to the design of complex circuits and systems. In this chapter we will learn about the design of combinatorial circuits. Topics include Design Hierarchy Top-Down Design CAD tools HDL Logic Synthesis

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 2 Logic Circuits These can be Sequential or Combinatorial. In Sequential Circuits the output, o(t) which is time dependent can take a value using the input at any time, t or prior to t. In Combinatorial Circuits the output, o(t) depends on the value of the input at the current time, t only. The parameters for optimizing combinatorial circuits are Logic Gates Boolean expressions Input variables Output variables Interconnections

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 3 Behavioral Description As mentioned earlier, a behavioral description specifies what a circuit does, but not how. Behavioral descriptions ALWAYS consist of two parts: An entity definition that identifies the signal lines that make up the inputs and outputs and the ports that interface the device with those signal lines. A signal line is any connection that can transmit one bit at a time. An entity can be referred to as a module consisting of specific tasks. A functional specification that specifies how the outputs are determined by the inputs. For an n-variable binary function, there are 2 n input sequences and a maximum of 2 # of input sequences possible output combinations.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 4 Relationship: Specifying and Implementing If some requirement is specified, then it must be designed. If it can be designed can we implement the idea behind it? If so, what is the most optimal strategy? Design Specification: What Analysis Implementation: HOW

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 5 System Specification: WHAT It is a functional or behavioral description of the system function Describes requirements/characteristics for its use. It could be in the form of English descriptions, entity definition, function tables, algebraic expressions, state diagrams, hardware description languages, etc. Should be complete (output for every input) As simple as possible Unambiguous: unique output given an input sequence No irrelevant details

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 6 System Implementation: HOW Describes how simpler modules are interconnected to implement the system. (Also referred to as structural description). The modules can be: electronic gates, logic gates, integrated circuits or whole processors.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 7 Design Hierarchy This uses a divide-and-conquer approach in building complex integrated circuits. It involves usage of block diagrams to represent circuits. Figure 3-2 (a) on page 90 of text shows a 9- input odd function circuit. X0X1X2X3X4X5X6X7X8X0X1X2X3X4X5X6X7X8 9-Input odd function Z0Z0 This circuit can be broken into smaller pieces or blocks. The schema for the other blocks are shown on page 90.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 8 Hierarchical Diagram for the 9-input odd function The detailed diagram of the 9-input odd function is shown on page 91 of the text. The total number of ways to complete a 9-input odd function is 1  4  2  4 = 32 9-input odd function 3-input odd function XOR NANDNAND Step 1 can be represented in only one way. Step 2 can be completed in 4 ways. Step 3 can be completed in 2 ways. Step 4 can be completed in 4 ways.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 9 Top Down Design This top down design concept is analogous from General-to-Specific of from Specific-to- General in Database Management Systems. The application requires text description, optimization, cost, performance, reliability, etc. The optimization process may include constraints in order to have a parsimonious structure. System Modules Gates, entities, etc Transistors, Contemporary Circuits Top Bottom

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 10 CAD Computer-aided-design uses blocks or functional blocks, libraries of graphic symbols to design integrated circuits. After completion the verification of outputs within a design is performed using a logic simulator. Optimization of designs is performed using a logic simulator.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 11 Hardware Description Language, HDL HDLs provide an alternative to schematics. HDLs have a structural description, i.e., they provides an interconnection to components. Such a structural description, i.e., which provides an interconnection to components (Netlist). A Netlist can be used as an input to logic simulation just as a schematic is used. HDL can be used to represent boolean equations, truth tables, arithmetical operations, etc. HDLs can be used at an intermediate level (RTL ). Register Transfer Languages, RTLs use a library of components to convert a description into an interconnection of primitive components that implement the circuit. Two very popular HDLs are VHDL and VERILOG.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 12 Logic Synthesis HDL Description of Circuit Translation Intermediate Representation Electronic, Speed, and Area Constraints Technology Library Preoptimization Optimization Technology Mapping Netlist

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 13 Design Space Any given design can be implemented using the design properties and available technology. A set of constraints (conditions) are applied during the implementation process. They are as follows: Gate Properties Levels of Integration Circuit Technologies Technology Parameters Positive and Negative Logic Design Trade-Offs A few of these constraints are discussed in the next set of slides.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 14 Levels of Integration Digital systems are constructed from components that have varying degrees of complexity. So far only the simplest digital components have been used, namely gates. Components can be classified broadly into four groups based on the "gate equivalency" of the digital components on the chip. Gate equivalency refers to the estimated number of gates that would be required to construct the digital system using discrete gates as the only components. Digital components are classified according to their gate equivalency: SSI (Small Scale Integration) refers to chips that have from 1 to 10 gates fabricated on their silicon substrates. Thus a single chip may have 6 inverters, 3 or 4 AND gates, or 1 or 2 OR gates depending on the number of inputs. MSI (Medium Scale Integration) refers to chips that have a gate equivalency of 10 to 100 gates per chip. This includes components such as adders, multiplexers, decoders, flip-flops, and registers. LSI (Large Scale Integration) includes components that have a gate equivalency of 500 to 5000 gates per chip, and includes devices such as arithmetic logic units (ALUs), read-only-memories (ROMs), and register files. VLSI (Very Large Scale Integration) includes components that have more than 10,000 gates/chip.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 15 Circuit Technologies The factors involved in circuit technology are high circuit density, high performance, low power consumption, etc. Currently CMOS, Complementary Metal Oxide Semiconductor technology is widely used. A few other types discussed in class are PMOS, VMOS, etc.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 16 Technology Parameters The most important parameters used to characterize and implementation technology are as follows: Fan-in specifies the number of inputs available on a gate. Fan-out specifies the number of standard loads driven by a gate output. Noise margin is the maximum allowable noise superimposed on a normal input value. Propagation delay is the time required for a change in value of a signal to propagate from input to output. Power dissipation is the power drawn from the power supply and consumed by the gate. This is dissipated as heat.

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 17 Positive and Negative Logic If we use a “0” or “1” logic state at the input or output levels, then the “1” logic level could be representing 5V or perhaps some other value. The “0” logic level could be representing 0V or perhaps some other value. The operation could be defined as positive logic and negative logic. This depends on how we select to voltage/current to indicate the “0” and “1” binary values. Positive logic occurs when the “1” logic level has a more positive value than the “0” logic level. Negative logic occurs when the “0” logic level has a more negative value than the “1” logic level. 5V 0V t ‘1’ logic level ‘0’ logic level 3V 0V t ‘1’ logic level ‘0’ logic level -7V

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 18 Design Trade-Offs How can we decide on the design? Consider the diagram shown here. Increasing the Fan-outs can increase the propagation delay, and perhaps cause overheating. Adding a buffer at F can reduce propagation delay whereby increasing the cost value? Look up possible circuit constraints on page 104 of text. A B Two Fan-ins F Gate 1Gate 2Gate 3 Three Fan-outs G

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 19 Design Procedure The following steps are involved in this procedure: Specification (specification or requirement for the circuit) Formulation (truth tables, boolean expressions between I/O) Optimization (two-level or multiple level) Technology Mapping (transforming the logic diagram or netlist to new diagram or providing a netlist for the resulting circuit using primitive gates) Verification (verify the correctness of the final design) Look up example on page 105 of text

CMPT150, Ch 3, Tariq Nuruddin, Fall 06, SFU 20 Programmable Implementation Technologies A programming logic device may have hundreds to millions of gates. The common types of programming logic devices are: ROM Programmable array logic (PAL) Programmable logic array (PLA) These are discussed on pages 126 to 132 of the text.