Logic Design Fundamentals - 1 Lecture L1.1

Logic Design Fundamentals - 1 Basic Gates Basic Combinational Circuits Basic Sequential Circuits

Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Y = !X Y = not X Y = ~X Basic Gates NOT X Y X Y Z XY X Y Z AND OR X Y Z X Y Z Z = X & Y Z = X and Y Z = X * Y Z = X # Y Z = X or Y Z = X + Y Any logic circuit can be created using only these three gates

NOT Gate Xnot Xnot not X = X X not X not not X Behavior: The output of a NOT gate is the inverse (one’s complement) of the input

AND Gate Behavior: The output of an AND gate is HIGH only if all inputs are HIGH Z = X(1) and X(2) and …. and X(n)

4-Input AND Gate 3-Level 2-Level Behavior: Z := '1'; for i in 1 to 4 loop Z := Z and X(i); end loop;

std_logic_1164.vhd TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); SUBTYPE std_logic IS resolved std_ulogic; SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')

std_logic_1164.vhd -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( | U X 0 1 Z W L H - | | ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | ); FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (and_table(l, r)); END "and";

OR Gate Behavior: The output of an OR gate is LOW only if all inputs are LOW Z = X(1) or X(2) or …. or X(n)

4-Input OR Gate 3-Level 2-Level Behavior: Z := '0'; for i in 1 to 4 loop Z := Z or X(i); end loop;

Exclusive-OR (XOR) Gate Behavior: The output of an XOR gate is HIGH only if the number of HIGH inputs is ODD Z = X(1) xor X(2) xor …. xor X(n)

2-Input XOR Gate XOR X Y Z Z = X $ Y Z = X xor Y Z = Y X Y Z Note: if Y = 0, Z = X if Y = 1, Z = not X Therefore, an XOR gate can be used as a controlled inverter

4-Input XOR Gate 3-Level 2-Level Behavior: Z := '0'; for i in 1 to 4 loop Z := Z xor X(i); end loop; Note: Z = 1 if the number of 1 inputs in ODD

NAND Gate (NOT-AND) Behavior: The output of an NAND gate is LOW only if all inputs are HIGH Z = not (X(1) and X(2) and …. and X(n))

2-Input NAND Gate NAND X Y Z Z = !(X & Y) Z = X nand Y Z = ~(X * Y) X Y Z

NOR Gate (NOT – OR) Behavior: The output of an NOR gate is HIGH only if all inputs are LOW Z = not (X(1) or X(2) or …. or X(n))

2 Input NOR Gate NOR X Y Z Z = !(X # Y) Z = X nor Y Z = ~(X + Y) X Y Z

NAND Gate X Y X Y Z Z Z = !(X & Y)Z = !X # !Y = X Y W Z X Y !X !Y Z

De Morgan’s Theorem-1 !(X & Y) = !X # !Y NOT all variables Change & to # and # to & NOT the result

NOR Gate X Y Z Z = !(X # Y) X Y Z X Y Z Z = !X & !Y X Y !X !Y Z

De Morgan’s Theorem-2 !(X # Y) = !X & !Y NOT all variables Change & to # and # to & NOT the result

De Morgan’s Theorem NOT all variables Change & to # and # to & NOT the result !X # !Y = !(!!X & !!Y) = !(X & Y) !(X & Y) = !!(!X # !Y) = !X # !Y !X & !Y = !(!!X # !!Y) = !(X # Y) !(X # Y) = !!(!X & !Y) = !X & !Y

Exclusive-NOR Gate XNOR (NOT – XOR) Behavior: The output of an XNOR gate is HIGH only if the number of HIGH inputs is EVEN Z = not (X(1) xor X(2) xor …. xor X(n))

2-Input XNOR Gate XNOR X Y Z Z = !(X $ Y) Z = X xnor Y Z = Y) Note: Z = 1 if X = Y Therefore, an XNOR gate can be used as an equality detector X Y Z

Implementing Gates Relays Normally open Normally closed A B C A B C A B C nMOS transistor A-B closed when C = 1 (normally open) pMOS transistor A-B closed when C = 0 (normally closed)

NOT Gate 5V XY Y = !X Y = not X X Y X Y

NOT Gate 5V XY Y = !X Y = not X X Y 0 1 X Y

NOT Gate 5V XY Y = !X Y = not X X Y 1 0 X Y

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NAND Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

NOR Gate X Y Z 5V X Y Z X Y Z

AND Gate X Y 5V Z NAND-NOT

OR Gate X Y 5V Z NOR-NOT