1. Logic Design Review – 1 Basic Gates Lecture L14.1 Verilog

2. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

3. Y = ~X not(Y,X) Basic Gates NOT X Y 0101 1010 X Y Z XY X Y Z AND OR X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 Z = X & Y and(Z,X,Y) Z = X | Y or(Z,X,Y) Any logic circuit can be created using only these three gates

4. NOT Gate X~X~X~~X = X X ~X ~~X 0 1 0 1 0 1 Behavior: The output of a NOT gate is the inverse (one’s complement) of the input

5. AND Gate Behavior: The output of an AND gate is HIGH only if all inputs are HIGH assign Z = X[1] & X[2] &... & X[n]; assign Z = &X; and(Z,X[1],X[2],...,X[n]);

6. 4-Input AND Gate 3-Level 2-Level Behavior: Z = X[1]; for(i=2; i<=4; i++) Z = Z & X[i];

7. OR Gate Behavior: The output of an OR gate is LOW only if all inputs are LOW assign Z = X[1] | X[2] |... | X[n]; assign Z = |X; or(Z,X[1],X[2],...,X[n]);

8. 4-Input OR Gate 3-Level 2-Level Behavior: Z = X[1]; for(i=2; i<=4; i++) Z = Z | X[i];

9. Exclusive-OR (XOR) Gate Behavior: The output of an XOR gate is HIGH only if the number of HIGH inputs is ODD assign Z = X[1] ^ X[2] ^... ^ X[n]; assign Z = ^X; xor(Z,X[1],X[2],...,X[n]);

10. 2-Input XOR Gate XOR X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 Z = X ^ Y xor(Z,X,Y) X Y Z Note: if Y = 0, Z = X if Y = 1, Z = ~X Therefore, an XOR gate can be used as a controlled inverter

11. 4-Input XOR Gate 3-Level 2-Level Note: Z = 1 if the number of 1 inputs in ODD Behavior: Z = X[1]; for(i=2; i<=4; i++) Z = Z ^ X[i];

12. Exclusive-NOR Gate XNOR (NOT – XOR) Behavior: The output of an XNOR gate is HIGH only if the number of HIGH inputs is EVEN assign Z = ~(X[1] ^ X[2] ^... ^ X[n]); assign Z = ~^X; xnor(Z,X[1],X[2],...,X[n]);

13. 2-Input XNOR Gate XNOR X Y Z 0 0 1 0 1 0 1 0 0 1 1 1 Z = ~(X ^ Y) Z = X ~^ Y xnor(Z,X,Y) Note: Z = 1 if X = Y Therefore, an XNOR gate can be used as an equality detector X Y Z

14. NAND Gate (NOT-AND) Behavior: The output of an NAND gate is LOW only if all inputs are HIGH assign Z = ~(X[1] & X[2] &... & X[n]); assign Z = ~&X; nand(Z,X[1],X[2],...,X[n]);

15. 2-Input NAND Gate NAND X Y Z Z = ~(X & Y) Z = X ~& Y nand(Z,X,Y) X Y Z 0 0 1 0 1 1 1 0 1 1 1 0

16. NOR Gate (NOT – OR) Behavior: The output of an NOR gate is HIGH only if all inputs are LOW assign Z = ~(X[1] | X[2] |... | X[n]); assign Z = ~|X; nor(Z,X[1],X[2],...,X[n]);

17. 2 Input NOR Gate NOR X Y Z Z = ~(X | Y) Z = X ~| Y nor(Z,X,Y) X Y Z 0 0 1 0 1 0 1 0 0 1 1 0

18. module gates ( X,Z, Y ); input [4:1] X ; wire [4:1] X ; output [6:1] Z ; wire [6:1] Z ; output [6:1] Y ; wire [6:1] Y ; and(Z[6],X[1],X[2],X[3],X[4]); nand(Z[5],X[1],X[2],X[3],X[4]); or(Z[4],X[1],X[2],X[3],X[4]); nor(Z[3],X[1],X[2],X[3],X[4]); xor(Z[2],X[1],X[2],X[3],X[4]); xnor(Z[1],X[1],X[2],X[3],X[4]); assign Y[6] = &X; assign Y[5] = ~&X; assign Y[4] = |X; assign Y[3] = ~|X; assign Y[2] = ^X; assign Y[1] = ~^X; endmodule Gates.v Verilog gate level primitives Verilog reduction operators

19. assign Y[6] = &X; assign Y[5] = ~&X; assign Y[4] = |X; assign Y[3] = ~|X; assign Y[2] = ^X; assign Y[1] = ~^X; and(Z[6],X[1],... nand(Z[5],X[1],... or(Z[4],X[1],... nor(Z[3],X[1],... xor(Z[2],X[1],... xnor(Z[1],X[1],...

20. NAND Gate X Y X Y Z Z Z = ~(X & Y)Z = ~X | ~Y = X Y W Z 0 0 0 1 0 1 1 0 0 1 1 1 1 0 X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0

21. De Morgan’s Theorem-1 ~(X | Y) = ~X | ~Y NOT all variables Change & to | and | to & NOT the result

22. NOR Gate X Y Z Z = ~(X | Y) X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 X Y Z Z = ~X & ~Y X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0

23. De Morgan’s Theorem-2 ~(X | Y) = ~X & ~Y NOT all variables Change & to | and | to & NOT the result

24. De Morgan’s Theorem NOT all variables Change & to | and | to & NOT the result -------------------------------------------- ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y) ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y ~X & ~Y = ~(~~X | ~~Y) = ~(X | Y) ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y

25. module gates ( X,Z); input [4:1] X ; wire [4:1] X ; output [1:6] Z ; reg [1:6] Z ; integer i; // 4-input and gate always @(X) begin Z[1] = X[1]; for(i=2; i<=4; i=i+1) Z[1] = Z[1] & X[i]; end Behavior of multiple input gates

26. // 4-input nand gate -- DeMorgan's Theorem always @(X) begin Z[2] = ~X[1]; for(i=2; i<=4; i=i+1) Z[2] = Z[2] | ~X[i]; end =

27. // 4-input or gate always @(X) begin Z[3] = X[1]; for(i=2; i<=4; i=i+1) Z[3] = Z[3] | X[i]; end Behavior of multiple input gates // 4-input nor gate // DeMorgan's theorem always @(X) begin Z[4] = ~X[1]; for(i=2; i<=4; i=i+1) Z[4] = Z[4] & ~X[i]; end

28. // 4-input xor gate always @(X) begin Z[5] = X[1]; for(i=2; i<=4; i=i+1) Z[5] = Z[5] ^ X[i]; end Behavior of multiple input gates // 4-input xnor gate always @(X) begin Z[6] = X[1]; for(i=2; i<=4; i=i+1) Z[6] = Z[6] ~^ X[i]; end endmodule

29. and nand or nor xor xnor

30. Implementing Gates Relays Normally open Normally closed A B C A B C A B C nMOS transistor A-B closed when C = 1 (normally open) pMOS transistor A-B closed when C = 0 (normally closed)

31. NOT Gate 5V XY Y = ~X not(Y,X) X Y X Y 0101 1010

32. NOT Gate 5V XY X Y 0 1 X Y 0101 1010 Y = ~X not(Y,X)

33. NOT Gate 5V XY X Y 1 0 X Y 0101 1010 Y = ~X not(Y,X)

34. NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0

35. NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 0 0

36. NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 0 1

37. NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 1 0

38. NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 1 1

39. NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0

40. NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 0 0

41. NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 0 1

42. NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 1 0

43. NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 1 1

44. AND Gate X Y 5V Z NAND-NOT

45. OR Gate X Y 5V Z NOR-NOT