1. Basic Gates Discussion D2.1

2. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

3. Y = !X Y = not X Y = ~X Y = X' Basic Gates NOT X Y 0101 1010 X Y Z XY X Y Z AND OR X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 Z = X & Y Z = X and Y Z = X * Y Z = XY Z = X # Y Z = X or Y Z = X | Y Z = X + Y Any logic circuit can be created using only these three gates

4. NOT Gate Xnot Xnot not X = X X not X not not X 0 1 0 1 0 1 Behavior: The output of a NOT gate is the inverse (one’s complement) of the input

5. AND Gate Behavior: The output of an AND gate is HIGH only if all inputs are HIGH Z = X(1) and X(2) and …. and X(n)

6. 4-Input AND Gate 3-Level 2-Level Behavior: Z := '1'; for i in 1 to 4 loop Z := Z and X(i); end loop;

7. std_logic_1164.vhd TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); SUBTYPE std_logic IS resolved std_ulogic; SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')

8. std_logic_1164.vhd -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- --| U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | ); FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (and_table(l, r)); END "and";

9. OR Gate Behavior: The output of an OR gate is LOW only if all inputs are LOW Z = X(1) or X(2) or …. or X(n)

10. 4-Input OR Gate 3-Level 2-Level Behavior: Z := '0'; for i in 1 to 4 loop Z := Z or X(i); end loop;

11. Exclusive-OR (XOR) Gate Behavior: The output of an XOR gate is HIGH only if the number of HIGH inputs is ODD Z = X(1) xor X(2) xor …. xor X(n)

12. 2-Input XOR Gate XOR X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 Z = X $ Y Z = X ^ Y Z = X xor Y Z = X @ Y X Y Z Note: if Y = 0, Z = X if Y = 1, Z = not X Therefore, an XOR gate can be used as a controlled inverter

13. 4-Input XOR Gate 3-Level 2-Level Behavior: Z := '0'; for i in 1 to 4 loop Z := Z xor X(i); end loop; Note: Z = 1 if the number of 1 inputs in ODD

14. NAND Gate (NOT-AND) Behavior: The output of an NAND gate is LOW only if all inputs are HIGH Z = not (X(1) and X(2) and …. and X(n))

15. 2-Input NAND Gate NAND X Y Z Z = !(X & Y) Z = X nand Y Z = ~(X * Y) X Y Z 0 0 1 0 1 1 1 0 1 1 1 0

16. NOR Gate (NOT – OR) Behavior: The output of an NOR gate is HIGH only if all inputs are LOW Z = not (X(1) or X(2) or …. or X(n))

17. 2 Input NOR Gate NOR X Y Z Z = !(X # Y) Z = X nor Y Z = ~(X + Y) X Y Z 0 0 1 0 1 0 1 0 0 1 1 0

18. NAND Gate X Y X Y Z Z Z = (X * Y)'Z = X' + Y' = X Y W Z 0 0 0 1 0 1 1 0 0 1 1 1 1 0 X Y X' Y' Z 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0

19. De Morgan’s Theorem-1 (X * Y)' = X' + Y' NOT all variables Change * to + and + to * NOT the result

20. NOR Gate X Y Z Z = (X + Y)' X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 X Y Z Z = X' * Y' X Y X' Y' Z 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0

21. De Morgan’s Theorem-2 (X + Y)' = X' * Y' NOT all variables Change * to + and + to * NOT the result

22. Exclusive-NOR Gate XNOR (NOT – XOR) Behavior: The output of an XNOR gate is HIGH only if the number of HIGH inputs is EVEN Z = not (X(1) xor X(2) xor …. xor X(n))

23. 2-Input XNOR Gate XNOR X Y Z 0 0 1 0 1 0 1 0 0 1 1 1 Z = !(X $ Y) Z = X xnor Y Z = ~(X @ Y) Note: Z = 1 if X = Y Therefore, an XNOR gate can be used as an equality detector X Y Z

24. Behavior of multiple input gates andd: process(X) variable Y: STD_LOGIC; begin Y := '1'; for i in 0 to 3 loop Y := Y and X(i); end loop; Z(1) <= Y; end process;

25. Behavior of multiple input gates = -- 4-input nand gate -- DeMorgan's Theorem nandd: process(X) variable Y: STD_LOGIC; begin Y := not X(0); for i in 1 to 3 loop Y := Y or (not X(i)); end loop; Z(1) <= Y; end process;

26. Behavior of multiple input gates orr: process(X) variable Y: STD_LOGIC; begin Y := '0'; for i in 0 to 3 loop Y := Y or X(i); end loop; Z(3) <= Y; end process; norr: process(X) variable Y: STD_LOGIC; begin Y := not X(0); for i in 1 to 3 loop Y := Y and (not X(i)); end loop; Z(4) <= Y; end process;

27. xorr: process(X) variable Y: STD_LOGIC; begin Y := X(0); for i in 1 to 3 loop Y := Y xor X(i); end loop; Z(5) <= Y; end process; xnorr: process(X) variable Y: STD_LOGIC; begin Y := X(0); for i in 1 to 3 loop Y := Y xnor X(i); end loop; Z(6) <= Y; end process; Behavior of multiple input gates

28. and nand or nor xor xnor