Fischer 08 1 Analog to Digital Converters Nyquist-Rate ADCs  Flash ADCs  Sub-Ranging ADCs  Folding ADCs  Pipelined ADCs  Successive Approximation (Algorithmic) ADCs  Integrating (serial) ADCs Oversampling ADCs  Delta-Sigma based ADCs

Fischer 08 2 Conversion Principles

Fischer 08 3 ADC Architectures  Flash ADCs: High speed, but large area and high power dissipation. Suitable for low-medium resolution (6-10 bit).  Sub-Ranging ADCs: Require exponentially fewer comparators than Flash ADCs. Hence, they consume less silicon area and less power.  Pipelined ADCs: Medium-high resolution with good speed. The trade- offs are latency and power.  Successive Approximation ADCs: Moderate speed with medium- high resolution (8-14 bit). Compact implementation.  Integrating ADCs or Ramp ADCs: Low speed but high resolution. Simple circuitry.  Delta-Sigma based ADCs: Moderate bandwidth due to oversampling, but very high resolution thanks to oversampling and noise shaping.

Fischer 08 4 Performance Limitations 1 Thermal Noise LimitationClock Jitter (Aperture) Limitation Normalized Noise Powers: Limiting Condition:  n-Bit ADC  Sinusoidal Input  Swing: ±1[V]  f max = ½ f conv System Definitions Maximum Resolution: f in =½f conv

Fischer 08 5 Performance Limitations 2  Selection of ADC Architecture is driven by Application Displays Audio Sonar Ultra Sound Video Wireless Communications Seismology

Fischer 08 6 Parallel or Flash ADCs Conceptual Circuit

Fischer 08 7 Sub-Ranging ADCs Half-Flash or Two-Step ADC

Fischer 08 8 Folding ADCs Principle Configuration … 2 n1 Sub-Ranges

Fischer 08 9 Folding Processor Example: 2-Bit Folding Circuit ( 2 n-1 +1)Io for n-Bit 2Io

Fischer Successive Approx. ADCs Concept Implementation

Fischer DAC Realization 1 (Voltage Mode)

Fischer DAC Realization 2 Spread Reduction through R-2R Ladder

Fischer DAC Realization 3 Charge-Redistribution Circuit Pros  Insensitive w.r.t. Op-amp Gain  Offset (1/f Noise) compensated Cons  Requires non-overlapping Clock  High Element Spread  Area  Output requires S&H valid only during  2

Fischer DAC Realization 4 Spread Reduction through capacitive Voltage Division valid only during  2 Spread=2 n/2 Example: 8-Bit ADC

Fischer DAC Realization 5 Charge-Redistribution Circuit with Unity-Gain Amplifier Pros  Voltage divider reduces spread  Buffer  low output impedance  No clock required Cons  Parasitic cap causes gain error  High Op-amp common mode input required  No amplifier offset compensation Amplifier Input Cap. Cp  Gain Error: є G =-Cp/16C 16/15C Spread=½2 n/2 Example: 8-Bit ADC

Fischer DAC8 with Unity-Gain Amplifier Sub-range Output (4 LSBs) 00.5u2u1.5u2.5u3.5u4.5u5.5u6.5u3u4u5u6u1u Amplifier Output 6.5u00.5u2u1.5u2.5u3.5u4.5u5.5u3u4u5u6u1u

Fischer DAC Realization 6 Current Mode Implementation

Fischer Current Cell & Floor Plan Unit Current Cell Symmetrical Current Cell Placement Current summing RailIout Cascode Current Source Switching Devices Array of 256 Cells R

Fischer DAC Implementation Layout of 10-Bit Current-Mode DAC ( 0.5  m CMOS) Current summing Rails

Fischer Modified SA Algorithm 1 Idea: Replace DAC by an Accumulator  Consecutively divide Ref by 2

Fischer Modified SA Algorithm 2 First cycle only Accumulator Idea: Maintain Comparator Reference (½ FS=Gnd)  Double previous Accumulator Output

Fischer SC Implementation SC Implementation of modified SA ADC

Fischer Timing Diagram

Fischer Offset Compensated Circuit Offset Compensated SC Implementation

Fischer Building Blocks 1 DC Gain77 dB Gain- bandwidth 104 CL= 1.5 pF Power 1.3 mW Output Swing 4 V p-p Transconductance Amplifier

Fischer Building Blocks 2 Power 0.5 mW Resolution > 0.5 mV Settling Time 3 ns Latched CMOS Comparator

Fischer Layout of 8-Bit ADC 165  m (0.5  m CMOS)

Fischer Spice Simulation (Bsim3) 8-Bit ADC: fclk=10MHz  fconv=1.25MHz

Fischer Pipelined ADCs Pipelined modified SA or Algorithmic ADC Pros  Offset (1/f Noise) compensated  Minimum C-spread  One conversion every clock period Cons  Matching errors  digital correction for n>8  Clock feed-through very critical  High amplifier slew rate required

Fischer Integrating or Serial ADCs Dual Slope ADC Concept Constant Ramp Prop. to Input Ramp Using 2 N /k samples requires Ref = FS/k  reduced Integrator Constant (Element Spread) N represents digital equivalent of analog Input

Fischer SC Dual-Slope ADC 10-Bit Dual-Slope ADC

Fischer ADC Testing Types of Tests  Static Testing  Dynamic Testing  In static testing, the input varies slowly to reveal the actual code transitions.  Yields INL, DNL, Gain and Offset Error.  Dynamic testing shows the response of the circuit to rapidly changing signals. This reveals settling errors and other dynamic effects such as inter-modulation products, clock-feed-trough, etc. Circuit Under Test Output Input Clock

Fischer Performance Metrics 1 Error Types  Offset  Gain  DNL  INL  Missing Codes IDEAL ADC Static Errors

Fischer Performance Metrics 2 Frequency Domain Characterization Ideal n-Bit ADC: SNR = 6.02 x n [dB] fsig Amplitude

Fischer ADC Error Sources Static Errors  Element or Ratio Mismatches  Finite Op-amp Gain  Op-amp & Comparator Offsets  Deviations of Reference Dynamic Errors  Finite (Amplifier) Bandwidth  Op-amp & Comparator Slew Rate  Clock Feed-through  Noise (Resistors, Op-amps, switched Capacitors)  Intermodulation Products (Signal and Clock)

Fischer Static Testing Servo-loop Technique  Comparator, integrator, and ADC under test are in negative feedback loop to determine the analog signal level required for every digital code transition.  Integrator output represents equivalent analog value of digital output.  Transition values are used to generate input/output characteristic of ADC, which reveals static errors like Offset, Gain, DNL and INL.

Fischer Dynamic Testing Types of Dynamic Tests  Histogram or Code-Density Test  FFT Test  Sine Fitting Test Test Set-up

Fischer Histogram or Code-Density Test  DNL appears as deviation of bin height from ideal value.  Integral nonlinearity (INL) is cumulative sum (integral) of DNL.  Offset is manifested by a horizontal shift of curve.  Gain error shows as horizontal compression or decompression of curve.

Fischer Histogram Test Pros and Cons of Histogram Test  Histogram test provides information on each code transition.  DNL errors may be concealed due to random noise in circuit.  Input frequency must be selected carefully to avoid missing codes (f clk /f in must be non-integer ratio).  Input Swing is critical (cover full range)  Requires a large number of conversions (o 2 n x 1,000).

Fischer Simulated Histogram Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset

Fischer FFT Test Pros and Cons of FFT Test  Offers quantitative Information on output Noise, Signal- to-Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR) and Harmonic Distortion (SNDR).  FFT test requires fewer conversions than histogram test.  Complete characterization requires multiple tests with various input frequencies.  Does not reveal actual code conversions

Fischer Simulated FFT Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset SFDR=60 dB SNDR=49 dB  ENOB=7.85