Penn ESE534 Spring2014 -- Mehta & DeHon 1 ESE534 Computer Organization Day 6: February 12, 2014 Energy, Power, Reliability.

Slides:



Advertisements
Similar presentations
Topics Electrical properties of static combinational gates:
Advertisements

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 23: April 10, 2013 Statistical Static Timing Analysis.
Caltech CS184a Fall DeHon1 CS184a: Computer Architecture (Structures and Organization) Day6: October 11, 2000 Instruction Taxonomy VLSI Scaling.
8/29/06 and 8/31/06 ELEC / Lecture 3 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5970/6970) Low Voltage.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 23: April 22, 2009 Statistical Static Timing Analysis.
CS 7810 Lecture 12 Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors D. Brooks et al. IEEE Micro, Nov/Dec.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 14: March 19, 2008 Statistical Static Timing Analysis.
Design and Implementation of VLSI Systems (EN0160)
Penn ESE Spring DeHon 1 ESE (ESE534): Computer Organization Day 6: January 29, 2007 VLSI Scaling.
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 18: Scaling Theory Prof. Sherief Reda Division of Engineering, Brown University.
Lesson 1 Introduction – “Is there a limit ?” Transistors – “CMOS building blocks” Physics, Cross section and Layout Views.
CSCE 612: VLSI System Design Instructor: Jason D. Bakos.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 22: April 11, 2011 Statistical Static Timing Analysis.
Penn ESE Spring DeHon 1 ESE (ESE534): Computer Organization Day 7: January 31, 2007 Energy and Power.
Fall 06, Sep 14 ELEC / Lecture 5 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (Formerly ELEC / )
Lecture 5 – Power Prof. Luke Theogarajan
Spring 2007EE130 Lecture 39, Slide 1 Lecture #39 ANNOUNCEMENTS Late projects will be accepted –by 1:10PM Monday 4/30: 20 pt penalty –by 1:10PM Friday 5/4:
Lecture 7: Power.
Advanced Computing and Information Systems laboratory Device Variability Impact on Logic Gate Failure Rates Erin Taylor and José Fortes Department of Electrical.
6.893: Advanced VLSI Computer Architecture, September 28, 2000, Lecture 4, Slide 1. © Krste Asanovic Krste Asanovic
1 VLSI and Computer Architecture Trends ECE 25 Fall 2012.
*F. Adamu-Lema, G. Roy, A. R. Brown, A. Asenov and S. Roy
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 16, 2013 Energy and Power.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 11: October 1, 2010 Variation.
ESE Spring DeHon 1 ESE534: Computer Organization Day 19: April 7, 2014 Interconnect 5: Meshes.
Lecture 03: Fundamentals of Computer Design - Trends and Performance Kai Bu
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 28, 2011 MOS Transistor.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 15, 2014 Energy and Power.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 6, 2010 Scaling.
Basics of Energy & Power Dissipation Lecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 13, 2014 Energy and Power.
Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Normalized Comparison of Architectures.
ECE 124a/256c Advanced VLSI Design Forrest Brewer.
CSCE 613: Fundamentals of VLSI Chip Design Instructor: Jason D. Bakos.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 37: December 8, 2010 Adiabatic Amplification.
Short Channel Effects in MOSFET
Caltech CS184 Winter DeHon 1 CS184: Computer Architecture (Structure and Organization) Day 7: January 21, 2005 Energy and Power.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: September 27, 2013 Variation.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 24: April 22, 2015 Statistical Static Timing Analysis.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 14, 2013 Energy and Power.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 19, 2011 Energy and Power.
EE141 © Digital Integrated Circuits 2nd Devices 1 Lecture 6. CMOS Device (cont) ECE 407/507.
Basics of Energy & Power Dissipation
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 5: February 1, 2010 Memories.
Caltech CS184 Winter DeHon 1 CS184a: Computer Architecture (Structure and Organization) Day 6: January 19, 2005 VLSI Scaling.
Day 16: October 6, 2014 Inverter Performance
Trends in IC technology and design J. Christiansen CERN - EP/MIC
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 19, 2014 MOS Transistor.
FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Topics n Logic gate delay. n Logic gate power consumption. n Driving large loads.
Caltech CS184 Winter DeHon 1 CS184a: Computer Architecture (Structure and Organization) Day 6: January 22, 2003 VLSI Scaling.
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 6.1 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng.
Penn ESE534 Spring DeHon 1 ESE534 Computer Organization Day 19: March 28, 2012 Minimizing Energy.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 11: September 22, 2014 MOS Transistor.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 15: October 3, 2014 Scaling.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 12: October 3, 2011 Variation.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor.
CS203 – Advanced Computer Architecture
MOSFET #5 OUTLINE The MOSFET: Sub-threshold leakage current
Penn ESE534 Spring DeHon 1 ESE534 Computer Organization Day 8: February 10, 2010 Energy, Power, Reliability.
CS203 – Advanced Computer Architecture
ESE532: System-on-a-Chip Architecture
ESE534: Computer Organization
ESE532: System-on-a-Chip Architecture
Day 18: October 17, 2012 Energy and Power Optimization
VLSI design Short channel Effects in Deep Submicron CMOS
Day 12: October 1, 2012 Variation
ESE532: System-on-a-Chip Architecture
EE141 Chapter 3 VLSI Design The Devices March 28, 2003.
ESE534 Computer Organization
ELEC 7770 Advanced VLSI Design Spring 2014 VLSI Yield and Moore’s Law
Presentation transcript:

Penn ESE534 Spring Mehta & DeHon 1 ESE534 Computer Organization Day 6: February 12, 2014 Energy, Power, Reliability

Penn ESE534 Spring Mehta & DeHon 2 Today Energy tradeoffs Voltage limits and leakage Variations [more of the gory transistor equations…]

Penn ESE534 Spring Mehta & DeHon 3 At Issue Many now argue energy will be the ultimate scaling limit –(not lithography, costs, …) Proliferation of portable and handheld devices –…battery size and life biggest issues Cooling, energy costs may dominate cost of electronics –Even server room applications

Preclass 1 1GHz case –Voltage? –Energy per Operation? –Power required for 2 processors? 2GHz case –Voltage? –Energy per Operation? –Power required for 1 processor? Penn ESE534 Spring Mehta & DeHon 4

Preclass 1 Lesson What does Preclass 1 result tell us? Penn ESE534 Spring Mehta & DeHon 5

6 Energy and Delay  gd =Q/I=(CV)/I I d,sat =(  C OX /2)(W/L)(V gs -V TH ) 2

Penn ESE534 Spring Mehta & DeHon 7 Energy/Delay Tradeoff E  V 2  gd  1/V We can trade speed for energy E×(  gd ) 2  constant Martin et al. Power-Aware Computing, Kluwer  gd =(CV)/I I d,sat  (V gs -V TH ) 2

Penn ESE534 Spring Mehta & DeHon 8 Area/Time Tradeoff Also have Area-Time tradeoffs –HW2 spatial vs temporal multipliers –See more next week Compensate slowdown with additional parallelism …trade Area for Energy  Architectural Option

Penn ESE534 Spring Mehta & DeHon 9 Question By how much can we reduce energy? What limits us?

Penn ESE534 Spring Mehta & DeHon 10 Challenge: Power

Penn ESE534 Spring Mehta & DeHon 11 Origin of Power Challenge Limited capacity to remove heat –~100W/cm 2 force air –1-10W/cm 2 ambient Transistors per chip grow at Moore’s Law rate = (1/F) 2 Energy/transistor must decrease at this rate to keep constant power density P/tr  CV 2 f E/tr  CV 2 –…but V scaling more slowly than F

Penn ESE534 Spring Mehta & DeHon 12 ITRS V dd Scaling: More slowly than F

Penn ESE534 Spring Mehta & DeHon 13 ITRS CV 2 Scaling: More slowly than (1/F) 2

Penn ESE534 Spring Mehta & DeHon 14 Origin of Power Challenge Transistors per chip grow at Moore’s Law rate = (1/F) 2 Energy/transistor must decrease at this rate to keep constant E/tr  CV 2

Penn ESE534 Spring Mehta & DeHon 15 Historical Power Scaling [Horowitz et al. / IEDM 2005]

Microprocessor Power Density Penn ESE534 Spring Mehta & DeHon 16 The Future of Computing Performance: Game Over or Next Level? National Academy Press, Watts

Intel Power Density Penn ESE534 Spring Mehta & DeHon 17

Penn ESE534 Spring Mehta & DeHon 18 Source: Carter/Intel 18 Power Limits Integration Impact

Power density is limiting scaling –Can already place more transistors on a chip than we can afford to turn on! Power is potential challenge/limiter for all future chips. –Only turn on small percentage of transistors? –Operate those transistors as much slower frequency? –Find a way to drop V dd ? Penn ESE534 Spring Mehta & DeHon 19

Penn ESE534 Spring Mehta & DeHon 20 How far can we reduce V dd ?

Penn ESE534 Spring Mehta & DeHon 21 Limits Ability to turn off the transistor Parameter Variations Noise (not covered today)

MOSFET Conduction Penn ESE534 Spring Mehta & DeHon 22 From:

Transistor Conduction Penn ESE534 Spring Mehta & DeHon 23 Three regions –Subthreshold (V gs <V TH ) –Linear (V gs >V TH ) and (V ds < (V gs -V TH )) –Saturation (V gs >V TH ) and (V ds > (V gs -V TH ))

Saturation Region Penn ESE534 Spring Mehta & DeHon 24 I ds,sat =(  C OX /2)(W/L)(V gs -V TH ) 2 (V gs >V TH ) (V ds > (V gs -V TH ))

Linear Region Penn ESE534 Spring Mehta & DeHon 25 I ds,lin =(  C OX )(W/L)((V gs -V TH )V ds -(V ds ) 2 /2) (V gs >V TH ) (V ds < (V gs -V TH ))

Penn ESE534 Spring Mehta & DeHon 26 Subthreshold Region (V gs <V TH ) [Frank, IBM J. R&D v46n2/3p235]

Operating a Transistor Concerned about I on and I off I on drive (saturation) current for charging –Determines speed: T gd = CV/I I off leakage current –Determines leakage power/energy: P leak = V×I leak E leak = V×I leak ×T cycle Penn ESE534 Spring Mehta & DeHon 27

Penn ESE534 Spring Mehta & DeHon 28 Leakage To avoid leakage want I off very small Switch V from V dd to 0 V gs in off state is 0 (V gs <V TH )

Penn ESE534 Spring Mehta & DeHon 29 Leakage S  90mV for single gate S  70mV for double gate For lowest leakage, want S small, V TH large 4 orders of magnitude I VT /I off  V TH >280mV Leakage limits V TH in turn limits V dd

How maximize I on /I off ? Maximize I on /I off – for given V dd ? E sw  CV 2 Get to pick V TH, V dd Penn ESE534 Spring Mehta & DeHon 30 I d,lin =(  C OX )(W/L)(V gs -V TH )V ds -(V ds ) 2 /2 I d,sat =(  C OX /2)(W/L)(V gs -V TH ) 2

Preclass 2 E = E sw + E leak E leak = V×I leak ×T cycle E sw  CV 2 I chip-leak = N devices ×I tr-leak Penn ESE534 Spring Mehta & DeHon 31

Preclass 2 E leak (V) ? T cycle (V)? Penn ESE534 Spring Mehta & DeHon 32

In Class Assign calculations –SIMD – each student computes for a different Voltage Collect results on board Group: Identify minimum energy point and discuss Penn ESE534 Spring Mehta & DeHon 33

Values VT(v)Esw(V)Eleak(V)E(V) E E E E E E E E E E E E E E E E E E E E-074E E E E E E E E E E E E E E E E E E-118.1E E-10 Penn ESE534 Spring Mehta & DeHon 34

Graph for In Class Penn ESE534 Spring Mehta & DeHon 35

Impact Subthreshold slope prevents us from scaling voltage down arbitrarily. Induces a minimum operating energy. Penn ESE534 Spring Mehta & DeHon 36

Penn ESE534 Spring Mehta & DeHon 37 Challenge: Variation

Penn ESE534 Spring Mehta & DeHon 38 Statistical Dopant Count and Placement [Bernstein et al, IBM JRD 2006]

Penn ESE534 Spring Mehta & DeHon 39 V th 65nm [Bernstein et al, IBM JRD 2006]

Penn ESE534 Spring Mehta & DeHon 40 Variation Fewer dopants, atoms  increasing Variation How do we deal with variation? 40 % variation in V TH (From ITRS prediction)

Penn ESE534 Spring Mehta & DeHon 41 Impact of Variation? Higher V TH ? –Not drive as strongly  slower –I d,sat  (V gs -V TH ) 2 Lower V TH ? –Not turn off as well  leaks more

Penn ESE534 Spring Mehta & DeHon 42 Variation Margin for expected variation Must assume V TH can be any value in range Probability Distribution V TH I on,min =I on ( Vth,max ) I d,sat  (V gs -V TH ) 2 V gs = V dd

Penn ESE534 Spring Mehta & DeHon 43 Margining Must raise V dd to increase drive strength Increase energy Probability Distribution V TH I on,min =I on ( Vth,max ) I d,sat  (V gs -V TH ) 2 V gs = V dd

Penn ESE534 Spring Mehta & DeHon 44 Variation Increasing variation forces higher voltages –On top of our leakage limits 44

Penn ESE534 Spring Mehta & DeHon 45 Margins growing due to increasing variation Margined value may be worse than older technology? Variations Probability Distribution Delay New Old

Penn ESE534 Spring Mehta & DeHon 46 End of Energy Scaling? [Bol et al., IEEE TR VLSI Sys 17(10):1508—1519] Black nominal Grey with variation

Chips Growing Larger chips (billions of transistors)  sample further out on distribution curve Penn ESE534 Spring Mehta & DeHon 47 From:

Penn ESE534 Spring Mehta & DeHon 48 Big Ideas Can trade time for energy –… area for energy Variation and leakage limit voltage scaling Power major limiter going forward –Can put more transistors on a chip than can switch Continued scaling demands –Deal with noisier components High variation … other noise sources

Admin Homework 2 due Tonight Reading for Monday on web Homework 3 due next Wednesday Penn ESE534 Spring Mehta & DeHon 49