Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003

2/36 Integrated Circuits Laboratory Faculty of EngineeringObjectives Learn the digital design flow starting from VHDL down to physical device verification. Be familiar with the basics of downloading a design into an FPGA and testing it. Learn Mentor Graphics Tools: - FPGA Advantage 5.x : - HDL Designer Series (Design Entry) - ModelSim (Simulation) - Leonardo Spectrum (Synthesis) Learn Xilinx Tools: - ISE Alliance (Placement and Routing) - iMPACT (Design Downloading into FPGA)

3/36 Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow HDL Designer Series (Design Entry) Download design to FPGA chip Design Architect (Schematic editing) ENIREAD & SG (Format conversion) (Schematic generation) Xilinx Alliance (FPGA Implementation) ModelSim (VHDL Simulation) FPGAASIC Leonardo Spectrum (FPGA or ASIC synthesis) VHDL netlist and SDF file for timing simulation VHDL netlist & VITAL Post synthesis verification Testing fail

4/36 Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow ASIC GDSII format to foundry Mach TA/PA (Timing and Power analysis) QuickSim (Digital simulation with delays) SPICE netlist IC station (Autoplace, Autoroute, DRC, LVS, netlist and parasitics extraction) DVE (Viewpoints generation) fail

5/36 Integrated Circuits Laboratory Faculty of Engineering Design Entry Using HDL Designer Series. First step is to create a design library. Design entry can either be Top-Down or Bottom-Up. Five different design entry methods are available: - VHDL / Verilog - Truth Table - Flow Charts - State Machines - Block Diagrams

6/36 Integrated Circuits Laboratory Faculty of Engineering Creating the Design Library (1) Design Entry 1. Run HDL Designer Series: > Start > All Programs > FPGA Advantage 5.x > Design > HDL Designer

7/36 Integrated Circuits Laboratory Faculty of Engineering Creating the Design Library (2) Design Entry Library Folder Library Name Press OK and Open Library to create designs

8/36 Integrated Circuits Laboratory Faculty of Engineering Creating the Design Design Entry

9/36 Integrated Circuits Laboratory Faculty of Engineering VHDL Entry (1) Design Entry

10/36 Integrated Circuits Laboratory Faculty of Engineering VHDL Entry (2) Design Entry Entity Name Library Name Architecture Name

11/36 Integrated Circuits Laboratory Faculty of Engineering VHDL Entry (3) Entity is written here Architecture is written here Design Entry Save

12/36 Integrated Circuits Laboratory Faculty of Engineering Truth Table Entry (1) Blue = Input Yellow = Output Right click to add or remove columns Design Entry

13/36 Integrated Circuits Laboratory Faculty of Engineering Truth Table Entry (2) Design Entry Enter required inputs and outputs Save

14/36 Integrated Circuits Laboratory Faculty of Engineering Truth Table Entry (3) Design Entry Library Name Entity Name Architecture Name Yet an entity is still required

15/36 Integrated Circuits Laboratory Faculty of Engineering Truth Table Entry (4) Design Entry

16/36 Integrated Circuits Laboratory Faculty of Engineering Truth Table Entry (6) Design Entry Library Name Truth Table Entity Name

17/36 Integrated Circuits Laboratory Faculty of Engineering Truth Table Entry (7) Design Entry

18/36 Integrated Circuits Laboratory Faculty of Engineering Truth Table Entry (8) Generate HDL Design Entry

19/36 Integrated Circuits Laboratory Faculty of Engineering Flow Chart Entry Design Entry Save Generate HDL Flow End Point Action Stat Point An Entity is required

20/36 Integrated Circuits Laboratory Faculty of Engineering State Diagram Entry Mainly Used for Controllers (Finite State Machines “FSM”) Design Entry Add state Start state 1 st one added Double click to add action Double click to add transition condition Add transition Generate HDL

21/36 Integrated Circuits Laboratory Faculty of Engineering Block Diagram Entry (1) Design Entry Block Diagram Editor Adding a block (for Top-Down designs) Adding a component (for Bottom-Up designs) Adding a moduleware (a library of VHDL blocks) Connectors I/O ports

22/36 Integrated Circuits Laboratory Faculty of Engineering Block Diagram Entry (2) Adding a component Design Entry Browse for your libraries here Browse for your components here Then drag to your Block diagram

23/36 Integrated Circuits Laboratory Faculty of Engineering Block Diagram Entry (3) Adding a modulware Design Entry

24/36 Integrated Circuits Laboratory Faculty of Engineering Block Diagram Entry (4) Design Entry Example of a Block Diagram

25/36 Integrated Circuits Laboratory Faculty of Engineering Test Benches Test benches are generated automatically as a block diagram with a tester and a block under test. The tester is a VHDL file with the entity already specified, only the test waveforms are required. Design Entry

26/36 Integrated Circuits Laboratory Faculty of EngineeringSimulation Using ModelSim. The created testbench can be used. Test Waveforms can be created within the program. Outputs can be checked either as waveforms or as a list of numbers.

27/36 Integrated Circuits Laboratory Faculty of Engineering Starting ModelSim Select the design to be simulated and then press Compilation is done and then ModelSim starts. Simulation

28/36 Integrated Circuits Laboratory Faculty of Engineering ModelSim Windows Simulation

29/36 Integrated Circuits Laboratory Faculty of Engineering Using ModelSim (1) Simulation

30/36 Integrated Circuits Laboratory Faculty of Engineering Using ModelSim (2) Simulation

31/36 Integrated Circuits Laboratory Faculty of Engineering Using ModelSim (3) Simulation Select a signal and either use Force for a specific input or Clock for a periodic signal

32/36 Integrated Circuits Laboratory Faculty of Engineering Using ModelSim (4) Simulation Time of simulation in ns Run simulation

33/36 Integrated Circuits Laboratory Faculty of EngineeringSynthesis Using Leonardo Spectrum. A technology dependent step. Either ASICs or FPGAs can be targeted. Various output formats can be obtained (VHDL/SDF/EDIF)

34/36 Integrated Circuits Laboratory Faculty of Engineering Running Leonardo Spectrum Synthesis Click on the synthesizer button Select your design unit

35/36 Integrated Circuits Laboratory Faculty of Engineering Adjusting Synthesis Flow Synthesis Choose your device family Choose your device Choose your speed grade Choose your wiring table Choose what to optimize for and whether to preserve hierarchy or not Check insert I/0 pads

36/36 Integrated Circuits Laboratory Faculty of Engineering Generating the EDIF File Synthesis Press Run Flow The EDIF file is created in this path

37/36 Integrated Circuits Laboratory Faculty of Engineering Other Outputs (1) Synthesis RTL SchematicTechnology Schematic

38/36 Integrated Circuits Laboratory Faculty of Engineering Other Outputs (2) Synthesis VHDL & SDF Area Report

39/36 Integrated Circuits Laboratory Faculty of Engineering Xilinx ISE4.2i Flow The input to the flow is the EDIF file from Leonardo Spectrum. The output is a bit file to be downloaded into the FPGA. Steps are: - Mapping the design blocks into the FPGA design units. - Placement and Rouing of these units. - Genration of the bit file and downloading it to the FPGA. An FPGA programmer kit must be present, connected to the PC and with a manual at hand to know pins configuration.

40/36 Integrated Circuits Laboratory Faculty of Engineering Creating a New Project (1) Design Implementation

41/36 Integrated Circuits Laboratory Faculty of Engineering Creating a New Project (2) Design Implementation Insert the name of the project Insert the path you want to create the project in Add data related to device family, the device itself, and the design flow used

42/36 Integrated Circuits Laboratory Faculty of Engineering Creating a New Project (3) Design Implementation Choose whether to add the EDIF netlist or to add a copy from it

43/36 Integrated Circuits Laboratory Faculty of Engineering Implementing the Design Design Implementation There are 3 steps for implementing the design: 1.Translating the EDIF netlist into primitives. 2.Mapping these primitives into their technology dependent counterpart. 3.Placing and routing these technology primitives.

44/36 Integrated Circuits Laboratory Faculty of Engineering Translating the Design (1) Design Implementation Translates the EDIF and gives a report declaring success of translation or gives warnings and errors. Generates a post translation model that can be in VHDL format for a first step back annotation

45/36 Integrated Circuits Laboratory Faculty of Engineering Right click on this tab Choose properties Translating the Design (2) Design Implementation Choose VHDL Format VHDL File Name

46/36 Integrated Circuits Laboratory Faculty of Engineering Mapping the Design Design Implementation Maps the primitives into technology primitives and generates a report. Generates a VHDL as before.

47/36 Integrated Circuits Laboratory Faculty of Engineering Placement and Routing of the Design Design Implementation

48/36 Integrated Circuits Laboratory Faculty of Engineering Programming the FPGA Design Implementation Generates the programming bit file for the FPGA Generates a file to be loaded into the PROM (if present in the kit) Downloads the design into the FPGA (iMPACT software)

49/36 Integrated Circuits Laboratory Faculty of EngineeringThanks Special thanks go to 1.Eng. Sameh Talal (Aiat Co.) 2.Eng. Ahmed Mohsen For their help in preparing the material for this presentation.