Voltus IC Power Integrity Solution Break-through in Power Signoff Jerry Zhao Product Marketing Director Power Sign-off Products, SSV Nov 21st, 2013

Agenda 1. Introduction – Challenges and Cadence Solution 2. Voltus - Performance, Capacity and Accuracy 3. Voltus and Design Closure 4. Summary

Design Challenges in Mobile Computing Era Mobile Devices Require Low Power Extending battery life Increasing device reliability Design Complexity Increases in Low Power ICs Advanced design techniques Increasing IP content and functionality Tighter design margins Power Integrity is Critical for Successful Design Signoff Occurs late in the design cycle Impacts timing and physical design closure Complexity in Power Signoff Grows as Design Complexity Increases

Power Solutions Have not Kept Pace with Designer’s Requirements Time Required for Power Analysis is Increasing due to Growing design complexity and size More complex analysis requirements Current Solutions don’t Consider the Impact of Power on Timing Closure New Challenges in 3DIC Technology Thermal breakdown Complete power integrity analysis from chip to package to system Designers Require New Technologies for Power Signoff

What Did Cadence Announce in Nov. 12th? Voltus™ IC Power Integrity Solution Break-through technology in power integrity analysis and signoff Up to 10X faster performance over existing solutions Most accurate electrical design signoff and closure solution Industry’s 1st power integrity tool integrated with static timing analysis Integration with Cadence digital & analog, package & board, and system level solutions for fast design closure TSMC 16nm FinFET Certification Customer Endorsements Freescale Semiconductor Integrated Device Technology Tilera Fastest Path to Design Signoff

The Voltus IC Power Integrity Solution Massively parallel execution Scalability across computer network Hierarchical analysis PERFORMANCE Early grid analysis in implementation Physically-aware grid optimization Chip and system co-design analysis CLOSURE SPICE-like accuracy Integrated power and timing signoff Foundry certification on advanced nodes ACCURACY

A Glance at Voltus Key Functionalities Power Calculation IR-Drop & EM De-Cap Power Switch IR-Aware STA (Tempus) Early Rail Analysis (EDI) Chip-PKG-PCB (Sigrity) Performance Accuracy Capacity Integration

Voltus Technology Advantages Performance, Capacity and Accuracy

Voltus - Exceptional Performance Innovation Through Parallelization Massively Parallel Execution Multi-threaded Distributed Processing Extra High Capacity Innovative hierarchical analysis Capacity up to 1B instances No Loss of Accuracy SPICE-accurate rail matrix solver Accurate power grid RC extraction Accurate instance power distribution … Voltus Massively Parallel Architecture Offers up to 10X Better Performance

Voltus Capacity Enablement Hierarchical Analysis Hierarchical methodology Block level power grid network captured by Power-Grid-View modeling (H-PGV) Top level circuitry combined with these H-PGVs to form a complete grid network “Top-down” or “Bottom-up” flows Targeting designs with 100+ million instances Silicon successes on 400+ M instances designs Capacity up to 1 Billion instances Productivity gains without loss of accuracy Performance improvement up to 4X vs. “flat” on large designs ECO flow at block level to fix EMIR issues through decap optimization, etc Hierarchical Analysis Flow Blk1 Power Grid Analysis ……… Blk N Power Grid Analysis H-PGV H-PGV H-PGV Top-level (Hierarchical Data) ECO Full Chip Power Signoff Analysis Accuracy Comparison 28mV (VDD) 27mV (VDD) 9mV (VSS) 9mV (VSS) Flat Hierarchical

Voltus Accuracy Foundations Advanced Algorithm Full scale SPICE-level PG matrix Grid simulation from SPICE engine Advanced parallel execution No loss of accuracy with multi-CPU Accurate power calculation Liberty, activity, signal propagation Embedded Cadence Sign-off Tools QRC: RC Extraction field solver accuracy on PG nets Tempus: Static Timing Signal propagation, timing window Spectre APS: Transistor Simulation PGV modeling, LDO Co-Sim Accurate IP Modeling Power-Grid-View (PGV) Cell intrinsic coupling cap PG extraction shown visibility inside Current char for multi-mode macro ECSM-Power SPICE-level current vs. NLPM Strong Eco-System Support TSMC Certification N16 FinFET & Design Reference Flow IP Suppliers on PGV library TSMC, Samsung, ARM EM Rules Support “qrcTechFile” format

TSMC 16nm FinFET Certification Recently certified by TSMC on 16nm FinFET (v0.5) TSMC OIP: San Jose, 10/1/2013 Both gate level (Voltus) and transistor level (VPS) FinFET stresses ElectroMigration Increased power density Reduced wire width Vertical current directions What does certification cover ? Power EM and Signal EM EM rules and accuracy IR-Drop accuracy What do EM rules include? Current direction Width/length dependencies Temperature rating factors : Cload charge discharge AC Current DC Current Power EM (AVG current)

Industry 1st Integrated Solution for Power and Timing Signoff Voltus – Accurate Electrical Signoff Next-generation, Unified Solution in Voltus + Tempus Power Integrity Directly Affects Timing Timing is most sensitive to power supply (VDD) Current segmented, point tool based solutions from multiple vendors are less accurate and cumbersome Leads to guard banding which increases pessimism in Static Timing Voltus + Tempus: New, Unified Signoff Solution Simultaneous power and timing analysis and closure Increases accuracy in STA by up to 3% Reduces timing pessimism More realistic voltage drop across the chip and its affect on timing Industry 1st Integrated Solution for Power and Timing Signoff

Voltus and Design Closure Power Grid Analysis, Optimization, ECO Flow, ….

Voltus – Fast Design Closure Complete Design Flow from Chip to System Tight Integration with IC Physical Implementation Early rail analysis & ECO: during power planning stages De-cap & ECO: IR-drop and leakage reduction Power gate switching& ECO: rush current, turn-on time Encounter Signoff Ecosystem Tempus APS Virtuoso Palladium Sigrity Chip-package-PCB Co-Simulation and Analysis Accurate power grid networks for chip and board Electrical-Thermal analysis 3DIC support, including CoWoS (2.5D) Productivity Improvements in IC Design Closure and System Design

Fully Places Instances (Power Calc and Distribution) Early Rail Analysis Bringing Power Grid Analysis and Design to Floorplanning Stage 3 Amp (PWL) 2 Amp (avg) 1Amp Fully Places Instances (Power Calc and Distribution) 0.4A EDI Floorplanning Std. Cell Placement CTS/Optimization Signal Routing ERA at Various Stage Voltus Engine Up to 10% vs. Sign off accuracy Flexible power-constraints specifications Interactive current region specification on not placed blocks Power calculation on place and/or routed blocks Early feedback for more efficient power grid network optimization Power grid width, straps, vias, epeats, spacing and IO/bump locations Power switch analysis to refine size and placement High Quality Power Grid Implementation for Faster Singoff Convergence

Logic/power rail within block Power Gate Switching Analysis & Optimization Switches, Rush Current and EDI ECO Logic/power rail within block Always-on VDD rail Switched VDD rail VSS rail ON Power Ramp-up OFF Ron Coarse-grain Up to 100’s of power domains Coarse-grain or fine-grain switches Comprehensive ramp-up sequence Steadystate analysis (static, dynamic) ON: switches impacts on power/EMIR OFF: power/leakage savings Power ramp-up analysis Rush current and turn-on time Impacting IR-Drop to surrounding blocks Power switch optimization Switches: sizes, numbers, locations ECO in EDI: upsizing, downsizing, or more switches inserted

De-coupling Cap Optimization Size and location of de-caps De-coupling caps and power grid Reducing localized dynamic IR-drop Adding leakage, slowing down recovery Calculating de-cap value User-defined voltage thresholds The required Q to compensate IR-drop Placement-aware de-cap optimization A universal voltage threshold Swapping filler cell with de-cap cell Timing-aware de-cap optimization A tighter voltage threshold for critical paths De-cap cells for no timing violation De-cap removal and ECO flows in EDI Optimization

Dynamic Power Analysis Voltus Vector-based EMIR Voltus Advantage - Palladium Dynamic Power Analysis Real-world, Application-specific Stimulus VCD/TCF/FSDB Palladium® Dynamic Power Analysis Voltus Vector-based EMIR Power time Deep Cycle ‘What if’ Budget Palladium® Dynamic Power Analysis (DPA) Real test environment for realistic stimulus generation Deep cycle dynamic power analysis to identify peak power windows for the chip Output chip activities in zero-delay (VCD/TCF/FSDB) format Vector-based Voltus IR-drop and EM analysis Annotating TWF into DPA output to generate vectors with delays for Voltus Power vector profiling and peak power window power signoff Why consider DPA in Palladium? Users get a real test environment that provides more realistic stimulus to DUT – including longer executions that we call “Deep cycles”. As a result they get more accurate low power analysis results compared to simulation DPA is tightly integrated with RC for very accurate analysis – RC and EPS deliver the low level estimates that are accumulated by DPA at higher levels All this results in early access to Power Analysis within the RTL flow. It helps to identify architectural issues and offers an easy to use flow for analyzing power impacts of Software The main reason that hardware is used is that it provides fast time to power estimation results - weeks in simulation vs. hours with DPA  TI(Nice) reported 96% correlation. Well above 90% Accuracy Correlation with Silicon Measurement

Complete Cadence Power Integrity Solutions Full-chip Power Integrity Analysis for all Designs Voltus Virtuoso “Voltus” Full-chip Spectre APS/XPS Power Grid Views PGV “Voltus” Block & IP Virtuoso Power System (Transistor) The slide shows how the Voltus enables power integrity analysis for digital, custom and mixed signal designs On the left, the Voltus enables hierarchical power and power rail analysis, which allows us to efficiently support massive digital designs that are currently being created today. The key to this solution is the use of Power Grid Views, which are abstracted model of cells or blocks within the design. The Voltus is tightly integrated with the Encounter platform for digital implementation, which enables our customers with significant ease-of-use and efficiency improvements over competitive standalone solutions For custom designs created in Virtuoso, the Virtuoso enables transistor-level power rail and electromigration analysis, together with electromigration verification for signal nets. Once a block has been analyzed using Virtuoso Power System, a Power Grid View of the block can be created, which enables hierarchical, full-chip power analysis in Voltus for mixed signal SoC designs that include both digital and custom components Digital (SoC) IR drop and EM Custom/Analog IR Drop & EM Mixed Signal Accurate Transistor EMIR Analysis, High Quality Analog IP Grid Modeling

Chip-Package-Board Varieties Chip-Package-Board Co-Simulation Integrated Voltus and Sigrity Design Flows 2D 2.5D (Si Interposer) 3D (TSV) Chip-Package-Board Varieties Sigrity package model generation XtractIM: broadband SPICE format PowerSI: S-parameter format Voltus die model generation Broadband SPICE format Frequency and time domains Single-port and N-port (up to 100’s) Sigrity MCP interface Model Connection Protocol Name- based or location-based Complete power integrity solutions Chip: Voltus + package model System: PowerDC + die model Voltus Sigrity Package Model Die-Model

Electrical-Thermal Co-Simulation Power Temperature Leakage Chip-PKG-PCB Temperature Temperature Map Power Map Voltus PowerDC PKG PCB Chip 3 Chip 2 Chip 1 Thermal Co-Simulation Thermal Runaway Positive feedback among chip’s Temperature, leakage, and power dissipation Temperature dependent IR-drop and EM Thermal Simulation in “Voltus + PowerDC” Voltus output: temperature and location dependent “Power Map” file PowerDC computes detailed temperature distribution for Chip-PKG-PCB (T vs. time) Voltus reads back “Temperature Map” file for EMIR convergence Thermal view available in 2D/3D

Voltus – The New Standard in Power Signoff In Summary Voltus Accelerates Design Closure and Signoff Up to 10X faster than competing solutions Up to 1 billion instances in capacity Voltus and Tempus are integrated for more accurate electrical design closure Integration with other Cadence tools for fast and complete design closure Cadence Solves the Design Complexity Challenges in Power Signoff Enabling designers to meet their targets Enhanced performance, accuracy and design closure Voltus – The New Standard in Power Signoff