LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN A flexible stand-alone testbench for characterizing the front-end electronics for the CMS Preshower detector under LHC- like timing conditions Paul Aspell 1, David Barney 1, Yves Beaumont 1, Suhas Borkar 2, Aruna Borkar 2, Jacques Domeniconi 1, David Futyan 1, Apollo Go 3, Suresh Lalwani 2, Carmen Palomares 1, Remi Prunier 4, Serge Reynaud 1 1 CERN, Geneva, Switzerland 2 Bhabha Atomic Research Centre, Mumbai, India 3 National Central University, Chung-Li, Taiwan 4 French Cooperant at CERN

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Overview of Presentation The CMS Preshower Requirements of the front-end electronics PACE-2 architecture Test setup –Requirements –Hardware –Software –Results Future & perspectives

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN CMS Preshower – physics motivation Main physics goal of CMS is search for SM Higgs If m H < 150 GeV/c 2 best chance is through 2  decay But large reducible background from  0 faking single photons Idea of Preshower: Single incident photon Two closely-spaced incident photons

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN CMS Preshower – physical location

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN CMS Preshower – mechanical layout 63mm 32 strips Front-end electronics

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN PACE-2 Architecture PACE-2 is an assembly of two chips in DMILL 0.8  m BiCMOS technology Delta Preamp with leakage current compensation Switched gain shaper. Low gain (0-400 MIPs) for physics, high gain (0-50 MIPs) for calibration Programmable biasing, modes of operation and calibration pulse PACE-AM 32 channels, 160 columns analogue pipeline. 3 samples per trigger into a 24-deep FIFO Programmable biasing, latency, modes of operation LVDS inputs for 40MHz clock, LV1, ReSynch etc. I 2 C input for programming of both PACE-AM and Delta

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN PACE-2 MCM Delta 3.5 x 6 mm 2 PACE AM 9.6 x 6.4 mm 2 Hybrid containing PACE2 Most outputs from PACE2 are for test purposes only!

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Design Verification Testbench – basic requirements Flexible –Many digital and analogue functions to test –Capable of tracing the cause of possible malfunctions Fast - need to simulate LHC-like running conditions –40 MHz clock –Fast control signals for Delta and PACE-AM via LVDS –Multiple triggers (programmable) Slow control –I 2 C interface for register loading etc. DAQ system on-board Cheap! Want to replace NIM/CAMAC/VME with a small standalone unit, controllable via LabView –Produce multiple copies of system for different labs, beam tests etc. Prototype for Production Test system – need to evaluate ~7000 PACE for the Preshower

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Motherboard Architecture

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN PACE Test Motherboard – side 1 Mitsubishi M16C  controller PACE-2 Hybrid Altera FLEX 10k FPGA FIFOs (2 x 8k,8-bit) RS232 AD bit 40 MHz ADC Delay lines

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Programming Environment Multithreaded application running on M16C microcontroller –Text-string communication from PC via RS232 –Structure of command is: s, e.g. S42D1 – read FLEX control register –User interface built using LabView 6i Task IDFunctionTask IDFunction 0Scan i 2 c address11Read ADC FIFO status 1Write to i 2 c12Read 1 trigger block 2Read from i 2 c13Write to DAC 3Write to FLEX14Read software version 4Read from FLEX15Toggle echo 5Set one bit in FLEX16Set echo to ON 6Clear one bit in FLEX17Set echo to OFF 7Toggle one bit in FLEX18Clear M16C circular buffer 8Write to delay line19Toggle offset to ASCII 9Read from delay line20Set RS232 baud rate 10General reset21-25Various tasks for Poisson random trigger generation

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Modes of Operation Motherboard as a “Master” with internal trigger generation –Normal operation mode for design evaluation Motherboard as a “Master” with external trigger generation –Useful for testing system with a silicon sensor attached, stimulated by an IR laser or a radioactive source Motherboard as a “slave” with external trigger generation –Useful to synchronize two motherboards together (e.g. in a beam test)

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Internal (Motherboard) Triggering Modes FLEX FPGA can be programmed to generate a burst of up to 16 triggers (“CalBurst”) by specifying the time (in # of clocks, up to 65535) between triggers Each “trigger” is actually two pulses: –Calib – telling the PACE to generate an internal electronic injection signal –LV1 – sent clocks after the Calib 6 different internal trigger modes: –Mode 0: Single ReSynch, single CalBurst –Mode 1: Free running ReSynch (specifying period), each followed by a single CalBurst –Mode 2: Single ReSynch, free running CalBursts (specifying period between CalBursts) –Mode 3: Free running ReSynch, free running CalBursts –Mode 4: Single ReSynch, CalBurst on demand (by toggling one bit in the FLEX control register) –Mode 5: Free running ReSynch, CalBurst on demand

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN FLEX FPGA Control Via LabView

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN PACE Register loading/reading

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Design Verification – Digital Part Test I 2 C addressing on PACE-AM –If this doesn’t work, stop testing Load/verify registers on Delta and PACE-AM –Can also read the default register values at power-on Put PACE into “Run” mode (set one bit in the PACE-AM control register) Set internal trigger to mode 0 (single ReSynch, single CalBurst) Examine basic digital signals via connectors on hybrids –ADC FIFO empty flag –Multiplexer signals –Data-valid signal –Loop signals (signify number of columns in the memory that are currently blocked) –Memory addresses of blocked columns (timing of trigger relative to a ReSynch can be used to determine a required column – and thus check that all columns are working)

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Test of Skipping Mechanism Test 121 Skip 3 cells ☺ Test 2312 Skip 6 cells ☺ Test Skip 9 cells ☺ Test Skip 12 cells ☺ Test Skip 15 cells ☺ Test Skip 18 cells ☺ Test Skip 21 cells ☹ Numbers refer to “trigger number” 1. Send N consecutive triggers to block a complete region in memory 2. Send one further trigger such that 2 of the 3 cells are before the blocked region and the 3 rd is after the blocked region 3. Test to see if the memory addresses read-out are ok 4. See how many cells can be skipped (before and after irradiation)

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Design Verification – DAC Optimization First need to set biases/currents on Delta and PACE- AM to default values –Loop over possible DAC values (i.e. set the appropriate registers via I 2 C) and measure analogue outputs (from test pads) using the ADCs on the M16C –Use plots to determine best DAC settings and apply them

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Design Verification – Analogue Output For one trigger the analogue output comprises 96 sequential values – multiplexed output for 32 channels for each of three time-samples Can look at this with an oscilloscope or after the ADC using the PC Charge injection into channel 11, pedestals subtracted

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Design Verification + Production Testing Most remaining design verification tests concern the analogue performance –Injection seen in all channels? –Gain uniformity between channels –Pedestal uniformity through the memory and between channels –Dynamic range (in both gains) –Timing scan to determine signal shape after the pre- amp/shaper stage Using the delay lines All of these tests are also incorporated into our systematic testing procedure……

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Production Testing Front Panel

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Testing charge injection on all channels

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Timing curves – using all 3 samples Time sample 1 Result Time sample 3 Time sample 2

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Linearity – High Gain, High Precision ~ 0 mips~ 7 mips ~11 mips ~16 mips

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Linearity Curves High Gain High prec. Low Gain High prec. High Gain Low prec. Low Gain Low prec.

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Future Production Testing At present to perform the complete set of tests on one PACE-2 assembly takes ~10 minutes –Speed limited by RS232 interface (115kbits/sec) –Next version of test system may use USB Speed ultimately limited by settling time for some tests, and by time taken for changing the chip (final version PACE-3 (0.25  m) will be a packaged assembly of the Delta and PACE-AM) –Perhaps will take ~2 minutes to test one assembly Need to test ~7000 assemblies (assuming 60% yield) Should note that currently we have ~65% yield with the DMILL version (~100 PACE-2 assemblies tested), and about half of the failures are due to problems with the I 2 C interface –In these cases the testing procedure is much shorter!

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Other Uses of Testbench – Beam Test In May 2002 two silicon sensors were placed in a proton/pion beam at PSI –Used PACE-2 as the front-end –Used our test bench as the control/DAQ system –Worked very well, although max trigger rate was only about 20 Hz (limited by ADC FIFOs on the motherboard and RS232 communication speed)

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Other Uses of Testbench – Irradiations Test digital/analogue performance in X-ray beam at CERN

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Testing other chips System is extremely flexible Changing connectors and adapting programs in the M16C & FPGA (and the LabView user interface) could allow the testing of similar devices – e.g. SCT, APV…..

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Summary and Conclusions A testbench has been developed for the CMS Preshower front-end electronics (PACE) It is sufficiently flexible to allow testing of all analogue and digital functionality Software has been developed to allow systematic testing of large quantities of chips Next version of the testbench will incorporate a higher-speed communication to a PC, allowing production testing of ~7000 PACE assemblies Further information, including system documentation and schematics can be found on the CMS Preshower web site: –

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Spare Slides

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN PACE-II Test Motherboard – side 2 Relays for switching input to ADCs on  controller

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Preshower Electronics Chain

LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN PACE-2 Signal shape etc. 160 columns 32 channels write pointerread pointer latency Sample Time 3 samples per trigger (LV1) are stored in the memory for each of the 32 input channels. These data are multiplexed to an ADC at 20 MHz