PradeepKumar S K Asst. Professor Dept. of ECE, KIT, TIPTUR. PradeepKumar S K, Asst.

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Presentation transcript:

PradeepKumar S K Asst. Professor Dept. of ECE, KIT, TIPTUR. PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur. 1

Why Standards? SoC components (IPs) have an interface to the outside world consisting of a set of pins responsible for sending/receiving addresses, data, control Number and functionality of pins must adhere to a specific interface standard Important for seamless integration of SoC IPs – helps avoid integration mismatches e.g. 1 - connecting IP with 32 data pins to a 30 bit data bus e.g. 2 - connecting IP supporting data bursts to a bus with no burst support Mismatches require development of “logic wrappers” at IP interfaces to ensure correct data transfers time consuming to create, reduce performance, take up area 2 PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

Why Standards? Interface standards define a specific data transfer protocol decide number and functionality of pins at IP interfaces make it easy to connect diverse IPs quickly Two categories of standards for SoC communication: Standard bus architectures define interface between IPs and bus architecture define (at least some) specifics of bus architecture that implements data transfer protocol Socket based bus interface standards define interface between IPs and bus architecture freedom w.r.t choice and implementation of bus architecture Ideally, designers want one standard to interconnect all IPs In reality, several competing standards have emerged 3 PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

4 Standard Bus Architectures AMBA 2.0, 3.0 (ARM) CoreConnect (IBM) Sonics Smart Interconnect (Sonics) STBus (STMicroelectronics) Wishbone (Opencores) Avalon (Altera) PI Bus (OMI) MARBLE (Univ. of Manchester) CoreFrame (PalmChip) … widely used PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

5 Bluetooth “Platform” SoC Processor Memory Controller Application Specific Logic Low-speed I/O and Support Logic System Bus / Hardware I/F PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

6 Simple System Busses The primary goal of a simple system bus is to allow software (running on a processor) to communicate with other hardware in the SoC There are many different implementation... but they are all very similar PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

7 Embedded Processor I/O RISC-based embedded processors communicate with external hardware using two simple instructions: –Load Operation: Copies a word of data from a specific address to a local register –Store Operation: Copies a word of data from a local register to a specific address The simple system bus is just a direct extension of this model PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

8 Embedded Processor I/O Software sets up the register with the address and data... Blocks decode addresses to see if they are the targets... Data transferred between register and hardware PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

9 AMBA Specification AMBA: Advanced Microcontroller Bus Architecture Created by ARM to enable standardized interfaces to their embedded processors Actually three standards: APB, AHB, and AXI Very commonly used for commercial IP cores NoCSimple BusComplex Bus PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

10PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur. AMBA 2.0

AHB Basic Transfer 11 Split ownership of Address and Data bus PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

AHB Basic Transfer 12 Data transfer with slave wait states PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

AHB Pipelining 13 Transaction pipelining increases bus bandwidth PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

AHB Architecture 14 centralized arbitration / decode 1 unidirectional address bus (HADDR) 2 unidirectional data buses (HWDATA, HRDATA) At any time only 1 active data bus PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

AHB Arbitration 15 HBREQ_M1 HBREQ_M2 HBREQ_M3 Arbiter Arbitration protocol is specified, but not the arbitration policy PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

16 Time for arbitration Time for handshaking Cost of Arbitration in AHB PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

17 Bursts cut down on arbitration, handshaking time, improving performance AHB Pipelined Burst Transfers PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

AHB Burst Types 18 Fixed length bursts Incremental bursts access sequential locations e.g. 0x64, 0x68, 0x6C, 0x70 for INCR4, transferring 4 byte data Wrapping bursts “wrap around” address if starting address is not aligned to total no. of bytes in transfer e.g. 0x64, 0x68, 0x6C, 0x60 for WRAP4, transferring 4 byte data PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

19 Improves bus utilization May cause deadlocks if not carefully implemented AHB Split Transfers PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

20 Bring on the complexity... CPU #1 CPU #2 IP Block #1 IP Block #2 IP Block #3 IP Block #4 PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

21 Bring on the complexity... Request CPU #1 CPU #2 IP Block #1 IP Block #2 IP Block #3 IP Block #4 PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

22 Bring on the complexity... Request Grant CPU #1 CPU #2 IP Block #1 IP Block #2 IP Block #3 IP Block #4 PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

23 Bring on the complexity... Request Grant Transaction CPU #1 CPU #2 IP Block #1 IP Block #2 IP Block #3 IP Block #4 PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

24 Bus Arbitration When multiple masters share a bus there must be some central resource to manage the bus: an arbiter Once there is competition for the bus, it is possible that it is not ready when you need it: backpressure Backpressure adds complexity and hurt performance PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

25 Request / Grant Protocol PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

26 Request / Grant Protocol Before a transaction a master makes a request to the central arbiter PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

27 Request / Grant Protocol Before a transaction a master makes a request to the central arbiter Eventually the request is granted PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

28 Request / Grant Protocol Before a transaction a master makes a request to the central arbiter Eventually the request is granted Then the transaction proceeds PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

29 Request / Grant Protocol Before a transaction a master makes a request to the central arbiter Eventually the request is granted Then the transaction proceeds Performance Impact PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

30 Pipelined Transactions To help improve bus efficiency the transactions on the bus can be pipelined This is really a simple implementation of multiple outstanding transactions The address for one transaction can be presented before the data from the previous transaction has been completed PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

31 Pipelined Transactions PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

32 Pipelined Transactions Transaction A Starts PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

33 Pipelined Transactions Transaction A Starts Transaction B Starts PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

34 Pipelined Transactions Transaction A Starts Transaction B Starts Transaction A Completes PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

35 Pipelined Transactions Transaction A Starts Transaction B Starts Transaction A Completes Notice backpressure PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

36 Advantages Relatively easy to add new blocks Still has the familiar bus structure Low hardware cost Bus arbitration “solves” many ordering problems PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

37 Disadvantages Busses that require arbitration: –must route signals to the arbitration logic and back –must find a “fair” way to share the bus –slaves are not always available => backpressure –difficult to provide performance guarantees... Still potentially a bandwidth bottleneck Still doesn’t scale well when blocks are added Multiple outstanding transactions not handled well - no ordering information PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

38 Networks-on-Chip (NoCs) PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

39 Networks-on-Chip It is clear that even with significant design effort the bus-style interconnect is not going to sufficient for large SoCs: –the physical implementation does not scale: bus fanout, loading, arbitration depth all reduce operating frequency –the available bandwidth does not scale: the single bus must be shared by all masters and slaves PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

40 Networks-on-Chip It is clear that even with significant design effort the bus-style interconnect is not going to sufficient for large SoCs: –the physical implementation does not scale: bus fanout, loading, arbitration depth all reduce operating frequency –the available bandwidth does not scale: the single bus must be shared by all masters and slaves Lets start again: Leverage research from data networking PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

41 What do we want? The SoCs of the future will: –have 100s of hardware blocks, –have billions of transistors, –have multiple processors, –have large wire-to-gate delay ratios, –handle large amounts of high-speed data, –need to support “plug-and-play” IP blocks Our NoC needs to be ready for these SoCs... PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

42 The Ideal Network What would the ideal network look like?: –Low area overhead –Simple implementation –High-speed operation –Low-latency –High-bandwidth –Operate at a constant frequency even with additional blocks –Increase available bandwidth as blocks are added –Provide performance guarantees –Have a “universal” interface PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

43 The Ideal Network What would the ideal network look like?: –Low area overhead –Simple implementation –High-speed operation –Low-latency –High-bandwidth –Operate at a constant frequency even with additional blocks –Increase available bandwidth as blocks are added –Provide performance guarantees –Have a “universal” interface These are competing requirements: Design a network that is the “best” fit. PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

44 What do we need to decide? Network Interface Network Protocol / Transaction Format Network Topology VLSI Implementation PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

45 Network Interface We want our network to be “plug-and-play” so industry standardization is key However the standard be universal enough to address many different needs AMBA AXI is an example of an attempt at this PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

46 AMBA AXI ARM added the AXI specification to Version 3.0 of the AMBA standard New approach: define the interface and leave the interconnect up to the designers Good plan since a specific bus implementation is no longer required It is possible to use AXI to build many different NoCs PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

47 AMBA AXI Interface divided into 5 channels: –Write Address –Write Data –Write Response –Read Address –Read Data/Response Each channel is independent and use two- way flow control PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

48 AMBA AXI Read Channels PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

49 AMBA AXI Read Channels Independent PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

50 AMBA AXI Read Channels Give me some data Independent PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

51 AMBA AXI Read Channels Give me some data Here you go Independent PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

52 AMBA AXI Read Channels Give me some data Here you go Independent channels synchronized with ID # or “tags” PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

53 AMBA AXI Write Channels PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

54 AMBA AXI Write Channels Independent PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

55 AMBA AXI Write Channels I’m sending data. Please store it. Independent PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

56 AMBA AXI Write Channels I’m sending data. Please store it. Here is the data. Independent PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

57 AMBA AXI Write Channels I’m sending data. Please store it. Here is the data. I received that data correctly. Independent PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

58 AMBA AXI Write Channels I’m sending data. Please store it. Here is the data. I received that data correctly. Independent channels synchronized with ID # or “tags” PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

59 AMBA AXI Flow-Control Information moves only when: –Source is Valid, and –Destination is Ready On each channel the master or slave can limit the flow Very flexible PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

60 AMBA AXI Flow-Control Information moves only when: –Source is Valid, and –Destination is Ready On each channel the master or slave can limit the flow Very flexible Transfer PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

61 AMBA AXI Flow-Control This definition of very independent, fully flow-controlled channels is very useful However, there is a potential problem: PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

62 AMBA AXI Flow-Control This definition of very independent, fully flow-controlled channels is very useful However, there is a potential problem: DEADLOCK PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

63 AMBA AXI Flow-Control This definition of very independent, fully flow-controlled channels is very useful However, there is a potential problem: DEADLOCK On a write transaction the master must not wait for AWREADY before asserting WVALID PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

64 AMBA AXI Read PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

65 AMBA AXI Read Read Address Channel Read Data Channel PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

66 AMBA AXI Write PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

67 AMBA AXI Write Write Address Channel Write Response Channel Write Data Channel PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

68 A True Interface Specification Because of the channel independence and the two-way flow-control the interface does not dictate the network protocol, transaction format, network topology, or VLSI implementation For example: –if you want to build a packet-based network, you can “backpressure” the data channel while you build the packet header from the address channel information, –you can use store-and-forward, or cut-through, –etc. PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

69 Network Protocol / Transaction Format There are many choice for network protocols and transactions formats: –circuit-switched : plan and provision a connection before communication starts –packet-switched : issues packets which compete for network resources –hybrids: schedule connectivity (dynamic or static) PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

70 Network Protocol / Transaction Format There are many choice for network protocols and transactions formats: –circuit-switched : plan and provision a connection before communication starts –packet-switched : issues packets which compete for network resources –hybrids: schedule connectivity (dynamic or static) There is still lots of research here.... PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

71 Network Topology How should your network elements be interconnected: –Fully Connected (N 2 ): high area cost, high performance –Mesh: low area cost, potential poor performance –Hypercube: medium area, traffic dependent performance –Fat-tree: medium area, traffic dependent performance –Torus: medium area, traffic dependent performance PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

72 Network Topology There is lots of research here.... PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

73 Network Topology - Caveat There has been a lot of research on topologies for NoCs, however it is important to realize that the performance of a topology is highly dependent on the traffic patterns! Traffic patterns in an SoC that you are designing yourself are NOT random, therefore much of the topology research is not applicable to most SoCs! PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

74 VLSI Implementation Once you have a topology there is still the mater of implementing it on your SoC There are many considerations: –Clocking: Synchronous, Asynchronous –Buffer Insertion: Trade-off power, area, performance –Register Insertion / Pipelining: Trade-off clock frequency, area, and latency –Packet Buffers: Trade-off area, latency and throughput Again, lots of research on-going... PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.

75 Bluetooth “Platform” SoC Processor Memory Controller Application Specific Logic Low-speed I/O and Support Logic System Bus / Hardware I/F PradeepKumar S K, Asst. Professor,Dept. of ECE, KIT,Tiptur.