1. ECE 456 Computer Architecture
Fall09
ECE 456 Computer Architecture
Lecture #3 - Function & Structure
Instructor: Dr. Honggang Wang

2. Administrative Issues (9/14/09, Mon.)
Fall09
Administrative Issues (9/14/09, Mon.)
Project proposal
due Monday, October 21
Homework #1
due Monday, September 30
Today’s topic
Review Lecture #2 (Interrupt)
Lecture #3
Dr. Wang
Lecture #2
Background Review Lecture

3. Review of Lecture #2 In the last lecture, we covered the
Fall09
Review of Lecture #2
In the last lecture, we covered the
number systems concepts and conversions (review)
concept of computer architecture & computer organization
von Neumann architecture
interrupts and multiple interrupts
contemporary computer architecture = von Neumann architecture + interrupts
Basicconcept of computer architecture and organization
Von Neumann architecture (3 key concepts)
Interrupts and multiple interrupts
Contemporary computer architecture is von Neumann architecture, plus interrupts
Dr. Wang
Lecture #2

4. Topics Concept of computer function & structure Function: Structure:
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Topics
Concept of computer function & structure
Function:
program view: instruction cycle
computer view: basic functions
Structure:
hierarchical system structure
interconnection structures: bus and multiple-bus
Dr. Wang
Lecture #2

5. Structure and Function
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Structure and Function
Structure is the way in which the components are interrelated
Function is the operation of each individual component as part of the structure
Dr. Wang
Lecture #2

6. Functions Computer view: basic functions
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Functions
Computer view: basic functions
Program view: instruction cycle
Dr. Wang
Lecture #2

7. Computer Basic Functions
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Computer Basic Functions
Data processing
Data storage
Data movement
input/output, data communications
Control
the control of the above three functions
control unit
Dr. Wang
Lecture #2

8. Computer Program Execution Function
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Computer Program Execution Function
Program execution: repeating the process of instruction execution
Instruction cycle:
Dr. Wang
Lecture #2

9. Instruction Cycle with Interrupts
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Computer Program Execution Function
Instruction Cycle with Interrupts
Fetch cycle
Execute cycle
Interrupt cycle
Dr. Wang
Lecture #2

10. Interrupt Cycle Dr. Wang Lecture #2 Fall09
In the following, we will focus on some details about the fetch cycle and
execute cycle.
Dr. Wang
Lecture #2

11. Instruction Fetch Cycle
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Computer Program Execution Function
Instruction Fetch Cycle
Processor fetches an instruction from a memory location pointed by PC
Unless told otherwise, the PC increments after each instruction fetch
Fetched instruction is loaded into IR
Processor interprets the instruction in IR and execute cycle begins
Dr. Wang
Lecture #2

12. Discussion Questions Under what situation,
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Discussion Questions
Under what situation,
the PC’s increment is not 1?
the PC is not incremented in sequence?
Dr. Wang
Lecture #2

13. Instruction Execute Cycle
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Computer Program Execution Function
Instruction Execute Cycle
Processor-memory
data transfer between CPU and memory
data storage
Processor-I/O
data transfer between CPU and I/O module
Data processing
arithmetic or logic operations
Control
alternation of instruction sequence
Combinatorial actions
Dr. Wang
Lecture #2

14. Example (1) Both data & instructions are stored in a 16-bit memory
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Computer Program Execution Function
Example (1)
Both data & instructions are stored in a 16-bit memory
Integer
Instruction
CPU registers: PC, IR, AC, MBR, MAR
Operation codes
0001: load AC from memory
0010: store AC to memory
0101: add to AC from memory 1 15 S 3 4 15
Opcode Address
Dr. Wang
Lecture #2

15. Example (2) M(940) + M(941) M(941) fetch execution
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Computer Program Execution Function
Example (2)
fetch
execution
M(940) + M(941)
M(941)
Dr. Wang
Lecture #2

16. How does the operation process look like if MAR and MBR are used?
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How does the operation process look like if MAR and MBR are used?
Step 1:
The PC contains 300, the address of the first instruction. This value is loaded in to the MAR.
The value in location 300 (which is the instruction with the value 1940 in hexadecimal) is loaded into the MBR, and the PC is incremented. These two steps can be done in parallel.
The value in the MBR is loaded into the IR.
Dr. Wang
Lecture #2

17. Steps 2 - 6 Step 2: Step 3 – Step 6???
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Steps 2 - 6
Step 2:
The address portion of the IR (940) is loaded into the MAR.
The value in location 940 is loaded into the MBR.
The value in the MBR is loaded into the AC.
Step 3 – Step 6???
Dr. Wang
Lecture #2

18. Instruction Cycle State Diagram
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Computer Program Execution Function
Instruction Cycle State Diagram
Dr. Wang
Lecture #2

19. Instruction Cycle State Diagram with Interrupts
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Computer Program Execution Function
Instruction Cycle State Diagram with Interrupts
Dr. Wang
Lecture #2

20. Agenda Concept of computer function & structure Function:
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Agenda
Concept of computer function & structure
Function:
basic functions
instruction cycle
Structure: the way in which the components are interrelated
hierarchical system structure
interconnection structures: bus and multiple-bus
Ok, so far we have discussed the concepts about function and structure
and we have looked detailedly at the computer functions, the basic functions including data processing, data storage, data movement, and control and the program execution function from the Program point of view. Specifically, we looked at the instruction cycle.
In the next part we will discuss about the computer structure in more detail.
Before we do that, let us have a 5-minute break.
Dr. Wang
Lecture #2

21. L1 L2 Computer L3 L4 communication lines peripherals Computer
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Hierarchical Structure
communication
lines L1
peripherals
Computer
Main
Memory
Input
/Output
Central Processing
Unit
Computer L2
Control Unit
ALU
Registers
CPU L3
Internal CU Bus CU
Registers
Decoders
Control
Memory
Sequencing
Logic
Control Unit L4
Dr. Wang
Lecture #2

22. Interconnection Structures
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Interconnection Structures
Interconnection structure: the collection of paths connecting the various modules
Bus / multiple-bus structures are the most common
Its design depends on the exchanges made between modules
Dr. Wang
Lecture #2

23. Bus Interconnection Structure
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Bus Interconnection Structure
Bus
Elements of bus design
Interconnection structure
Dr. Wang
Lecture #2

24. Bus A bus is a communication pathway connecting two or more devices
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Bus
A bus is a communication pathway connecting two or more devices
a shared transmission medium
usually broadcasts
transmits the signal of one device at a time
often consists of multiple separate communication lines
bus width: number of lines
A key characteristic of a bus is that it is a shared transmission medium. Also, the signal on a bus is usually broadcast, which means that a signal transmitted by any one device attached to the bus is available for reception by all other devices attached to this bus. Also, if the two devices try to transmit the signals during the same time period, their signals will overlap and become garbled. Thus, only one device can successfully transmit at a time over a bus. This is controlled by the CPU.
The last thing about the bus is that it often consists of multiple separate communications lines, or to say, multiple channels, so that the multiple-bit data can be transmitted over the bus at the same time, for example, an 8-bit unit of data can be transmitted over a bus with 8 channels simultaneously.
Typically, a system bus (connecting the major computer components) is composed of from about 50 to hundred of separate lines. Remember in our first lecture, we once talked about DEC PDP-8 as one important member of the 3rd generation of computers. We know that the PDP-8 used an omni-bus composed of 96 separate signal lines, used to carry control, address and data signals.
In the following we will look at some elements about the bus design.
First it’s about the type of the buses.
Dr. Wang
Lecture #2

25. Bus Interconnection Structure
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Bus Interconnection Structure
Bus
Elements of bus design
bus types
methods of arbitration
timing
bus width
Interconnection structure
Dr. Wang
Lecture #2

26. Bus Types (1) Multiplexed Dedicated Functional dedication
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Bus Types (1)
Multiplexed
data and address transmission share the same set of lines
using Address Valid Control line
pros & cons:
fewer lines, thus space/cost is saved
more complex control, potential performance reduction
Dedicated
Functional dedication
Physical dedication
The bus can be separated into two generic types: dedicated and multiplexed.
By multiplexed bus, we mean that the address and data information can be transmitted over the same set of lines using Address Valid Control line. At the beginning of a data transfer, the address is placed on the bus and the AVC line is activated. At this point, each module attached to the bus has a specified period of time to copy the address and determine if it’s the addressed module. The address is then remove from the bus, the then the same bus connections are used for the subsequent read or write data transfer.
The advantages of using time multiplexing is the use of fewer lines, which save space, and usually cost. But there are disadvantages, that is, more complex control circuitry is needed within each module, and because certain events that share the same lines cannot take place in parallel, thus, there is a potential reduction in the system performance.
Another type of the bus is a dedicated bus, which means that a bus is permanently assigned to either one function, or a physical subset of computer components. They are called functional dedication and Physical dedication, respectively. And we will examine each of them in detail.
Dr. Wang
Lecture #2

27. Bus Types (2): Functional Dedication
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Bus Types (2): Functional Dedication
The use of separate dedicated
data lines
address lines
control lines
A common example about the functional dedication is the use of separate data lines, address lines, and control lines…..
Dr. Wang
Lecture #2

28. Data Bus Moving data/instructions between system modules
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Data Bus
Moving data/instructions between system modules
Data bus width is a key determinant of system performance
Dr. Wang
Lecture #2

29. Address Bus Designate source or destination of data on data bus
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Address Bus
Designate source or destination of data on data bus
Address bus width determines the maximum memory capacity
Format:
higher-order bits for identifying a module on the bus
lower-order bits for identifying a location inside that module
example:
The address lines , collectively are called the address bus. They are used to identify the source or destination of the data on the data bus.For example, the CPU wishes to read a word from the memory, it will put the address of the desired word on the address lines.
And the address bus width will determine the maximum memory address space that a processor can directly access.
For example, intel 8080 has 16-bit address bus, then the processor can access
2^{16}=64 K address space.
Also, the address lines can address I/O ports, besides the memory locations. And typically, the higher-order bits are used to select a particular module on the bus, ad lower-order bits are used for identifying a location inside that module, for example, in this 8-bit address bus, if the highest-order bit is 0, which means that the address we will access is in a memory module, and the left 7 bits will identify which of the memory location we will access.
If it’s 1 then we will access an I/O module, and the left 7 bits will specify the port number of the I/O devices we will access.
A7: 0 - the memory module
1 - the I/O module A0
Dr. Wang
Lecture #2

30. Fall09
Control Bus
Control the access to and the use of the data lines and address lines
Control signals:
memory read/write
I/O read/write
transfer ACK
bus request/grant
interrupt request/ACK
clock & reset
Dr. Wang
Lecture #2

31. Bus Types (3): Physical Dedication
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Bus Types (3): Physical Dedication
The use of multiple buses, each of which connects only a subset of modules
Pros & cons:
less bus contention, high throughput
increased size & cost
I/O device
…...
I/O
Module
I/O
Module
I/O Bus
I/O device
Processor
Memory Bus
External
Memory
Main
Memory
Dr. Wang
Lecture #2

32. Method of Arbitration Centralized arbitration Distributed arbitration
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Method of Arbitration
Centralized arbitration
a bus controller / arbiter controls bus access
be separate or a part of processor
Distributed arbitration
each module has access control logic
all modules cooperate together to share the bus
Dr. Wang
Lecture #2

33. Timing Coordination of events on the bus
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Timing
Coordination of events on the bus
According to the way to determine the occurrence of one event on the bus,
synchronous timing
is determined by a clock
is simple to implement & test, but less flexible
asynchronous timing
follows and depends on the occurrence of a previous event
is flexible and can tolerate mixed rates and technologies
Dr. Wang
Lecture #2

34. Synchronous Timing (1) Control bus lines include a clock line
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Synchronous Timing (1)
Control bus lines include a clock line
a clock transmits a regular sequence of alternating 1s and 0s of equal duration upon it
a clock cycle: a single transmission of 1-0
all devices on bus can read it
All events start at the beginning of a clock cycle
As we just said, with syn timing, the occurrence of all events on the bus is determined by a clock. The control bus lines includes a clock line upon which a clock …….
A single 1-0 transmission is referred to as a clock cycle, and defines a time slot. And the clock cycle is usually characterized by a clock frequency . For example, if the clock frequency is 4MHZ, which means that the time duration for each clock cycle will be 1/4MHZ=250 ns.
All other devices on the bus can read the clock line and usually, all events start at the beginning of a clock cycle. In the following, we will look at the examples when system is performing syn read and write operations.
It’s deserved to talk about another concept here, that is
a bus cycle. It generally defines a time slot/time duration for finishing a data transfer. It can be a clock cycle, or multiple clock cycles. You will encounter this concept in your first homework.
Dr. Wang
Lecture #2

35. Example: Timing for Synchronous Read & Write
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Example: Timing for Synchronous Read & Write 1
Dr. Wang
Lecture #2

36. Asynchronous Timing (1)
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Asynchronous Timing (1)
The occurrence of one event on the bus follows and depends on the occurrence
of a previous event
Dr. Wang
Lecture #2

37. Asynchronous Timing (2) Read Diagram
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Asynchronous Timing (2) Read Diagram
Dr. Wang
Lecture #2

38. Bus Width Data bus width affects system performance
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Bus Width
Data bus width affects system performance
the wider the data bus, the greater the number of bits transferred at one time
Address bus width affects memory capacity
the wider the address bus, the greater the range of memory locations that can be referenced
Dr. Wang
Lecture #2

39. Bus Interconnection Structure
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Bus Interconnection Structure
Bus
Elements of bus design
bus types
methods of arbitration
timing
bus width
Interconnection structure
Dr. Wang
Lecture #2

40. Single Bus Structure Advantages: simple, convenient, flexible
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Single Bus Structure
I/O device
CPU
Main
memory
I/O
module
…...
I/O
module
…...
I/O device
System Bus
Advantages: simple, convenient, flexible
Problems:
propagation delay
bottleneck
Originally, all the computer modules are attached to a single bus. Clearly, this kind of arrangement is simple and convenient. Also, this kind of bus structure is flexible because it allows modules to be plugged into the bus or removed from the bus easily to create various configurations.
But when a great number of devices are connected to the bus, the system performance will suffer because
1. In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. And such delay will determine the time it takes for devices to coordinate the use of the single bus. When the control of the bus has to be passed from one device to another frequently, those propagation delay will affect the system performance noticeably.
2. The second problem is that when the aggregate data transfer demand approaches the bus capacity, the bus can become a bottleneck.
Some approaches can be used to counter this problem to some extent, for example, increasing the data rate that the bus can carry, or using wider buses. But since the data rates generated by attached devices such as graphics and video controller, network interface are growing rapidly, it’s difficult for the single bus to keep pace with them. ( this is a race that a single bus is ultimately destined to lose)
Accordingly, many computer systems use multiple buses( generally laid out in a hierarchy)
Dr. Wang
Lecture #2

41. 2 - Bus Structure …... I/O Bus Processor Memory Bus I/O I/O Module
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2 - Bus Structure
I/O device
I/O
Module
I/O
Module
…...
I/O Bus
I/O device
Processor
Memory Bus
External
Memory:
Tape/Disk
Main
Memory
Dr. Wang
Lecture #2

42. 3 - Bus Structure (1) …... I/O Bus Processor I/O Module I/O Module
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3 - Bus Structure (1)
I/O device
I/O
Module
I/O
Module
…...
I/O Bus
I/O device
Processor
Data Bus
Memory
Memory
Instruction Bus
Dr. Wang
Lecture #2

43. 3 - Bus Structure (2): Mezzanine
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3 - Bus Structure (2): Mezzanine
Serial
Expansion (low-speed I/O) bus
Modem
Fax
Expansion
bus interface
High-speed I/O bus
SCSI/
LAN
Graphics/
Video
Bridge
System Bus
Memory
Processor
Dr. Wang
Lecture #2

44. 4 - Bus Structure …... …... Processor Input Bus I/O Module I/O Module
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4 - Bus Structure
…...
…...
Output
device
Output
device
Input
device
Input
device
Input Bus
I/O
Module
I/O
Module
Output Bus
Processor
Data Bus
Memory
Memory
Instruction Bus
Dr. Wang
Lecture #2

45. Summary of Lecture #3 Concept of computer function & structure
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Summary of Lecture #3
Concept of computer function & structure
Computer basic functions (4 kinds) and program execution function (instruction cycle)
4-level hierarchical computer structure
Computer interconnection structures
bus and its design elements
single and multiple bus structures
Dr. Wang
Lecture #2

46. Next Topics Memory Systems Characteristics of memory systems
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Next Topics
Memory Systems
Characteristics of memory systems
Memory hierarchy
Error correction in memory
More……
As we discussed before, the memory system is one of the most important component of the computer system. From this lecture, we will start to investigate the memory system. Specifically, in today’s lecture, we will
cover the following three parts.:……
Dr. Wang
Lecture #2

47. Things To Do Homework #1 Start the project ASAP!
Fall09
Things To Do
Homework #1
due 2pm Sep. 30, Monday
Start the project ASAP!
Check out the class website about
lecture notes
reading assignments
the project
Dr. Wang
Lecture #2