1. EE 107 Fall 2017 Lecture 7 Serial Buses – I2C Direct Memory Access
Networked Embedded Systems
Sachin Katti

2. I2C bus in our projects Communication with the camera Pros Cons
Read from the camera
Write to the camera
Pros
Simple wire connection
Two wires bus that can connect multiple peripherals with the MCU
Cons
Complexity is a bit higher

3. How to operate the camera?
I2C
register 1
register 2 ….
MCU
I2C
pixel array
FRAM
DMA
data
SPI
SD card

4. I2C Details Two lines Only two wires for connecting multiple devices
Serial data line (SDA)
Serial clock line (SCL)
Only two wires for connecting multiple devices

5. I2C Details Each I2C device recognized by a unique address
Each I2C device can be either a transmitter or receiver
I2C devices can be masters or slaves for a data transfer
Master (usually a microcontroller): Initiates a data transfer on the bus, generates the clock signals to permit that transfer, and terminates the transfer
Slave: Any device addressed by the master at that time

6. Bit Transfer on the I2C Bus
In normal data transfer, the data line only changes state when the clock is low
SDA
SCL
Data line stable; Data valid
Change of data allowed

7. Start and Stop Conditions
A transition of the data line while the clock line is high is defined as either a start or a stop condition.
Both start and stop conditions are generated by the bus master
The bus is considered busy after a start condition, until a stop condition occurs
Start Condition
Stop Condition
SCL
SDA

8. I2C Addressing Each node has a unique 7 (or 10) bit address
Peripherals often have fixed and programmable address portions
Addresses starting with 0000 or 1111 have special functions:-
Is a General Call Address
Is a Null (CBUS) Address
1111XXX Address Extension
Address Extension – Next Bytes are the Actual Address

9. I2C-Connected System
Example I2C-connected system with two microcontrollers
(Source: I2C Specification, Philips)

10. Master-Slave Relationships
Who is the master?
master-transmitters
master-receivers
Suppose microcontroller A wants to send information to microcontroller B
A (master) addresses B (slave)
A (master-transmitter), sends data to B (slave-receiver)
A terminates the transfer.
If microcontroller A wants to receive information from microcontroller B
A (master) addresses microcontroller B (slave)
A (master-receiver) receives data from B (slave-transmitter)
A terminates the transfer
In both cases, the master (microcontroller A) generates the timing and terminates the transfer

11. Exercise: How fast can I2C run?
How fast can you run it?
Assumptions
0’s are driven
1’s are “pulled up”
Some working figures
Rp = 10 kΩ
Ccap = 100 pF
VDD = 5 V
Vin_high = 3.5 V
Recall for RC circuit
Vcap(t) = VDD(1-e-t/τ)
Where τ = RC

12. Exercise: Bus bit rate vs Useful data rate
An I2C “transactions” involves the following bits
<S><A6:A0><R/W><A><D7:D0><A><F>
Which of these actually carries useful data?
So, if a bus runs at 400 kHz
What is the clock period?
What is the data throughput (i.e. data-bits/second)?
What is the bus “efficiency”?

13. Why do we need DMA?

14. Why do we need DMA?
Polling and Interrupt driven I/O concentrates on data transfer between the processor and I/O devices.
An instruction to transfer (mov datain,R0) only occurs after the processor determines that the I/O device is ready
Either by polling a status flag in the device interface or
Waits for the device to send an interrupt request.
Considerable overhead is incurred, because several program instructions must be executed for each data word transferred.

15. Why do we need DMA?
Instructions are needed to increment memory address and keeping track of work count.
With interrupts, additional overhead associated with saving and restoring the program counter and other state information.

16. Direct Memory Access (DMA)
To transfer large blocks of data at high speed, an alternative approach is used.
Blocks of data are transferred between an external device and the main memory, without continuous intervention by the processor.

17. DMA Controller DMA controller is part of the I/O interface.
Performs the functions that would normally be carried out by the processor when access main memory. For each word transferred, it provides the memory address and all the bus signals that control data transfer.

18. DMA Controller
Device wishing to perform DMA asserts the processors bus request signal.
Processor completes the current bus cycle and then asserts the bus grant signal to the device.
The device then asserts the bus grant ack signal.
The DMA device performs the transfer from the source to destination address.
Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal.
Processor acknowledges the bus release and resumes its bus cycles from the point it left off.

19. Use of DMA Controllers 2. DMA controller requests transfer to memory
RAM
GPIOs
DMA controller
Bus control logic
4. ACK
5. Interrupt when done
3. Data is transferred
Processor
Storage
1. CPU programs the DMA controller

20. How is OS involved
I/O operations are always performed by the OS in response to a request from an application program.
OS is also responsible for suspending the execution of one program and starting another.
OS puts the program that requested the transfer in the Blocked state,
initiates the DMA operation,
starts execution of another program.
When the transfer is complete, the DMA controller informs the processor by sending an interrupt request.
OS puts suspended program in the Runnable state so that it can be selected by the scheduler to continue execution.

21. Linear logical memory

22. Memory Architecture

23. Physical vs Virtual Memory
Two memory “spaces”
Virtual memory space ­ what the program “sees”
Physical memory space ­ what the program runs in (size of RAM)
Virtual memory requires
Dedicated hardware on CPU chip called Memory Mgmt Unit (MMU)
Cooperation between CPU hardware & operating system 0: 1:
M -1:
Main memory
Physical
address
(PA)
CPU 2: 3: 4: 5: 6: 7: 4
Data word 8:
...
MMU
Physical
address
(PA)
... 0: 1:
M-1:
Main memory
Virtual
(VA)
CPU 2: 3: 4: 5: 6: 7:
4100
Data word 4
CPU chip
Address
translation
Source: Bryant & O’Hallaron

24. Example: Virtual and Physical Address Space
0x0C
0x10
0x14
0x18
0x1C
add r1,r2,r3
0x00
0x04
0x08
0x0C
add r1,r2,r3
sub r2,r3,r4
sub r2,r3,r4
lw r2, 0x04
lw r2, 0x04
mult r3,r4,r5
mult r3,r4,r5
bne 0x00
add r10,r1,r2
sub r3,r4,r1
sw r5,0x0c

25. Cache coherency problems
Imagine a CPU equipped with a cache and an external memory that can be accessed directly by devices using DMA. When the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external memory version of X, assuming a write-back cache. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X.

26. Buffers and Arbitration
Most DMACs have a data storage buffer – network interfaces receive data from main memory at bus speed, send data onto network at network speed.
Bus Arbitration is needed to resolve conflicts with more than one device (2 DMACs or DMA and processor, etc..) try to use the bus to access main memory.

27. Bus Arbitration
Bus Master – the device that is allowed to initiate bus transfers on the bus at any given time. When the current master relinquishes control, another device can acquire this status.
Bus Arbitration – the process by which the next device to become bus master is selected and bus mastership is transferred to it.

28. Arbitration Approaches
Centralized – a single arbiter performs the arbitration.
Distributed – all devices participate in the selection of the next bus master.