1 Post RTL structures/flows targeting low power Srinivas R Jammula Intel Corporation Bangalore, India Naveen M Kumar Intel Corporation Bangalore, India Ambar Mukherji Intel Corporation Bangalore, India

DAC Motivation Power reduction is important for both high performance and battery life scenarios Power reduction is important for both high performance and battery life scenarios Traditionally, optimization steps in the design flow prioritize Timing than Power Traditionally, optimization steps in the design flow prioritize Timing than Power

DAC Scope of work  Our primary focus will be on synthesis to Tape-In  Addresses by choosing power friendly design structures  Complementing with new power friendly flows Our focus area

DAC Tech1 :: Latch movement in memory Moved latches from o/p to i/p of decoder Moved latches from o/p to i/p of decoder –2 n latches reduced to n latches Logic Synthesis Floorplan Placement Clock Tree Routing Post Route Opt Layout Finishing Before swap After swap Genram latch movement [RTL]

DAC Tech2 :: Sequential Cluster/multi-bit Logic Synthesis Floorplan Placement Clock Tree merge Clock Tree split Routing Post Route Opt Layout Finishing Seq clustering  flops pulled together – reduces clock routing  Single flops intercepted as Dual/Quad flops – clocks shared

DAC Tech3 :: Clocks L1/L2 swap & Low Vt Power friendly structure by swapping the clock-AND gate Power friendly structure by swapping the clock-AND gate Clock-tree with low-Vt cells instead of high-Vt Clock-tree with low-Vt cells instead of high-Vt Logic Synthesis Floorplan Placement Clock Tree merge Clock Tree split Routing Post Route Opt Layout Finishing Clock L1/L2 Swap Clk AND L2 CTS – After Swap Clk Buffer Clk Source L2 L1 CTS – Before Swap Flops L1 Clk And Clk Buffer Low Power Medium Power High Power

DAC Results Power reduction achieved in the entire design implementation phase Power reduction achieved in the entire design implementation phase –Enhanced performance per watt significantly Final quantification of all 3 techniques are tabulated below Final quantification of all 3 techniques are tabulated below Feature Clock Cdyn savings Design leakage Savings Timing impact technique 14%+0.25%Negligible technique 25%Negligible technique 315%-3%Negligible

DAC Summary/Next Steps Lot of scope to improve the current EDA tools to optimize for low power Lot of scope to improve the current EDA tools to optimize for low power Can these optimizations parameters become part of the cost function of the tool suite? Can these optimizations parameters become part of the cost function of the tool suite? –To get more global optimal solution There is scope for micro-architectural improvements There is scope for micro-architectural improvements –For ex: Clustering was effective due to native data flow –Improve the data path partitioning