Slide 1/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Charlie Brej, Jim Garside APT Group Manchester University.

Slides:

Advertisements

Similar presentations

Self-Timed Logic Timing complexity growing in digital design -Wiring delays can dominate timing analysis (increasing interdependence between logical and.

Advertisements

CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.

ECE C03 Lecture 71 Lecture 7 Delays and Timing in Multilevel Logic Synthesis Hai Zhou ECE 303 Advanced Digital Design Spring 2002.

Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev Dual-Rail Control Logic for Enhanced Circuit Robustness.

Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.

06/05/08 Biscotti: a Framework for Token-Flow based Asynchronous Systems Charlie Brej.

Self-Timed Systems Timing complexity growing in digital design -Wiring delays can dominate timing analysis (increasing interdependence between logical.

Introduction to CMOS VLSI Design Sequential Circuits.

VLSI Design EE 447/547 Sequential circuits 1 EE 447/547 VLSI Design Lecture 9: Sequential Circuits.

Introduction to CMOS VLSI Design Sequential Circuits

MICROELETTRONICA Sequential circuits Lection 7.

Lecture 11: Sequential Circuit Design. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits2 Outline  Sequencing  Sequencing Element Design.

Avshalom Elyada, Ran GinosarPipeline Synchronization 1 A Unique and Successfully Implemented Approach to the Synchronization Problem Based on the article.

Delay/Phase Regeneration Circuits Crescenzo D’Alessandro, Andrey Mokhov, Alex Bystrov, Alex Yakovlev Microelectronics Systems Design Group School of EECE.

Sequential Circuits. Outline  Floorplanning  Sequencing  Sequencing Element Design  Max and Min-Delay  Clock Skew  Time Borrowing  Two-Phase Clocking.

P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 1 Training Electrical.

1 Clockless Logic  Recap: Lookahead Pipelines  High-Capacity Pipelines.

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis EE4800 CMOS Digital IC Design & Analysis Lecture 11 Sequential Circuit Design Zhuo Feng.

Introduction to CMOS VLSI Design Clock Skew-tolerant circuits.

Clock Design Adopted from David Harris of Harvey Mudd College.

Embedding of Asynchronous Wave Pipelines into Synchronous Data Processing Stephan Hermanns, Sorin Alexander Huss University of Technology Darmstadt, Germany.

1/14 A Result Forwarding Unit for a Synthesisable Asynchronous Processor Luis Tarazona and Doug Edwards Advanced Processor Technologies Group School of.

© Ran Ginosar Lecture 3: Handshake Ckt Implementations 1 VLSI Architectures Lecture 3 S&F Ch. 5: Handshake Ckt Implementations.

Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No Chapter # 3: Multi-Level Combinational Logic 3.3 and Time Response.

Interfacing Processors and Peripherals Andreas Klappenecker CPSC321 Computer Architecture.

1 Clockless Logic Montek Singh Thu, Jan 13, 2004.

EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Latch-based Design.

ELEC 6200, Fall 07, Oct 24 Jiang: Async. Processor 1 Asynchronous Processor Design for ELEC 6200 by Wei Jiang.

Low Power Design for Wireless Sensor Networks Aki Happonen.

COMP Clockless Logic and Silicon Compilers Lecture 3

Multithreaded ASC Kevin Schaffer and Robert A. Walker ASC Processor Group Computer Science Department Kent State University.

Jordi Cortadella, Universitat Politècnica de Catalunya, Spain

ASYNC 2000 Eilat April Priority Arbiters Alex Bystrov David Kinniment Alex Yakovlev University of Newcastle upon Tyne, UK.

High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths Montek Singh and Steven Nowick Columbia University New York, USA

A 1.5 GHz AWP Elliptic Curve Crypto Chip O. Hauck, S. A. Huss ICSLAB TU Darmstadt A. Katoch Philips Research A 1.5 GHz AWP Elliptic Curve Crypto Chip O.

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.

Fall 2009 / Winter 2010 Ran Ginosar (

Lecture 11 MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines.

1 Clockless Logic: Dynamic Logic Pipelines (contd.)  Drawbacks of Williams’ PS0 Pipelines  Lookahead Pipelines.

Pipelining By Toan Nguyen.

Sequential Circuit  It is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its.

MOUSETRAP Ultra-High-Speed Transition-Signaling Asynchronous Pipelines Montek Singh & Steven M. Nowick Department of Computer Science Columbia University,

Paper review: High Speed Dynamic Asynchronous Pipeline: Self Precharging Style Name : Chi-Chuan Chuang Date : 2013/03/20.

CSIS 3510 Dr. Hoganson Bus Construction CSIS 3510 Computer Organization and Architecture Bus construction alternatives Bus control issues Bus arbitration.

Copyright © Silistix, all rights reserved Glitch Sensitivity and Defense of QDI NoC Links Sean Salisbury 18 May 2009.

Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints.

Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.

The Effects of Operating Conditions on Speed and Power of Replica – Based SRAM Circuits Nika Sharifvaghefi Nicholas Kumar EE241 - Spring 2012.

12004 MAPLD: 153Brej Early output logic and Anti-Tokens Charlie Brej APT Group Manchester University.

EE5970 Computer Engineering Seminar Spring 2012 Michigan Technological University Based on: A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating.

Reading Assignment: Rabaey: Chapter 9

1 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here.

Automatic Pipelining during Sequential Logic Synthesis Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona Joint work with Marc Galceran-Oms.

1 Practical Design and Performance Evaluation of Completion Detection Circuits Fu-Chiung Cheng Department of Computer Science Columbia University.

1 Recap: Lecture 4 Logic Implementation Styles:  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates, or “pass-transistor” logic.

1 Clockless Logic Montek Singh Thu, Mar 2, Review: Logic Gate Families  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates,

Interconnection Structures

Lecture 11: Sequential Circuit Design

Other Approaches.

Roadmap History Synchronized vs. Asynchronous overview How it works

Elec 2607 Digital Switching Circuits

Blame Passing for Analysis and Optimisation

High Performance Asynchronous Circuit Design and Application

Clockless Logic: Asynchronous Pipelines

Reduction in synchronisation in bundled data systems

Synchronous, Wave and Asynchronous pipeling

Wagging Logic: Moore's Law will eventually fix it

A Quasi-Delay-Insensitive Method to Overcome Transistor Variation

Early output logic and Anti-Tokens

Pipelining and Superscalar Techniques

Presentation transcript:

Slide 1/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Charlie Brej, Jim Garside APT Group Manchester University

Slide 2/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Outline  Asynchronous Logic  DIMS (Delay Insensitive Minterm Synthesis)  Early Output Logic  Guarding  Anti-Tokens  Collisions  Conclusions

Slide 3/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Asynchronous Latch RiRo AoAi Latch Req Ack

Slide 4/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Asynchronous Pipeline

Slide 5/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Asynchronous Pipeline Stall Wait!

Slide 6/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Dual-Rail Latch  Dual-Rail  00 = ‘ NULL ’  01 = 0  10 = 1  11 = Illegal  Return to ‘ NULL ’ Ri_0Ro_0 Ao Ai Latch Ri_1Ro_1

Slide 7/20IWLS 2003, May 30Early Output Logic with Anti-Tokens DIMS Logic C C C C

Slide 8/20IWLS 2003, May 30Early Output Logic with Anti-Tokens DIMS vs Early Output Logic C C C C Size:48 transistors Delay:4 inversions Size:12 transistors Delay:2 inversions

Slide 9/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Early Output Logic 0 1 0

Slide 10/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Guarding Problem:  Inputs  Late  Unnecessary  Acknowledge before ready Solution:  Validity signal (Vo) RiRo Ao Ai Latch Vo

Slide 11/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Early Output Guarding C

Slide 12/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Anti-Tokens Don ’ t:  Stall entire stage until late input arrives Do:  Stall the latch instead  Early ‘ Validity ’  Acknowledge before Data

Slide 13/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Anti-Token Generation 0 0 C A

Slide 14/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Anti-Token Propagation A A A C

Slide 15/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Token Pass TTT

Slide 16/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Anti-Token Pass AAA

Slide 17/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Token Anti-Token collision TTA

Slide 18/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Token Anti-Token collision 2 T?A

Slide 19/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Dual-Purpose Signals  Arbiter free  Req:  Token Request  Anti-Token Acknowledge  Ack:  Anti-Token Request  Token Acknowledge Req Ack

Slide 20/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Conclusions  New, fine-grain, asynchronous pipeline  Faster than DIMS (2x)  Smaller than DIMS (4x)  Lower power than DIMS  Some speed advantages over synchronous designs  Counterflow - no arbitration  Requires some timing assumptions

Slide 21/20IWLS 2003, May 30Early Output Logic with Anti-Tokens Timing Hazard example A 0 A 0 C