1. ELEC 6200, Fall 07, Oct 24 Jiang: Async. Processor 1 Asynchronous Processor Design for ELEC 6200 by Wei Jiang

2. ELEC 6200, Fall 07, Oct 24 2Jiang: Async. Processor Why Asynchronous Design Higher Performance Higher Performance No global clock No global clock proceed data at appropriate rate of environment proceed data at appropriate rate of environment Do not propagate local delay globally Do not propagate local delay globally Better Power Efficiency Better Power Efficiency Only activating functional units consume power Only activating functional units consume power Inactivated parts remain in “stand-by” state Inactivated parts remain in “stand-by” state No wasteful power dissipation by glitches No wasteful power dissipation by glitches Smaller Chip Size Smaller Chip Size Less high-frequency EMI components due to small amplitude and wide current peaks Less high-frequency EMI components due to small amplitude and wide current peaks

3. ELEC 6200, Fall 07, Oct 24 3Jiang: Async. Processor Sync vs. Async Pipeline Asynchronous Pipeline: No global clock No delay for clock transition

4. ELEC 6200, Fall 07, Oct 24 4Jiang: Async. Processor Dynamic Voltage Control Power supply is controlled by measuring the occupancy of input FIFO As FIFO fills the supply voltage will increase and the processor will operate faster to empty the FIFO

5. ELEC 6200, Fall 07, Oct 24 5Jiang: Async. Processor Asynchronous Circuit Design Level-sensitive/Four- phase signaling protocol simpler design Transition-sensitive/two- phase protocol: no “nonactive” state fewer transitions higher performance lower power dissipation

6. ELEC 6200, Fall 07, Oct 24 6Jiang: Async. Processor Asynchronous Interface Two-phase Pipeline handshake protocol Sender to ensure that all bits of the data bundle are valid prior to sending the Request event (local delay management); Receiver to accept the data bundle prior to sending its Acknowledge which will permit the Sender to remove the old data and place a new value on the data lines

7. ELEC 6200, Fall 07, Oct 24 7Jiang: Async. Processor Event Driven Pipeline Components must respond to input transitions (events) rather than logic levels Components must respond to input transitions (events) rather than logic levels Muller C-gate: o Muller C-gate: outputs a transition only when all inputs have experienced transitions changing their input levels Storage elements must respond identically to rising or falling transitions Storage elements must respond identically to rising or falling transitions

8. ELEC 6200, Fall 07, Oct 24 8Jiang: Async. Processor Asynchronous Storage Capture-Pass latch Capture-Pass latch Event on Capture line causes latch to hold input data Event on Capture line causes latch to hold input data Capture-done event indicates completion of capture operation Capture-done event indicates completion of capture operation Event on Pass line cause latch to return transparent state Event on Pass line cause latch to return transparent state Pass-done event indicates completion of pass operation Pass-done event indicates completion of pass operation Interconnect Capture-Pass latches using Muller C-gates to form Pipeline Interconnect Capture-Pass latches using Muller C-gates to form Pipeline

9. ELEC 6200, Fall 07, Oct 24 9Jiang: Async. Processor Prevention of Hazards Data Hazards Data Hazards An instruction depends on the results of a previous instruction still in the pipeline An instruction depends on the results of a previous instruction still in the pipeline Prevented by Register Locking mechanism: stall the instruction until write-back of register takes place Prevented by Register Locking mechanism: stall the instruction until write-back of register takes place Pipeline must support multiple asynchronous read/write operations Pipeline must support multiple asynchronous read/write operations Control Hazards Control Hazards The instructions after branch instruction are loaded into pipeline but may not be executed The instructions after branch instruction are loaded into pipeline but may not be executed Prevented by Delayed Branch mechanism: the next instructions is always executed Prevented by Delayed Branch mechanism: the next instructions is always executed

10. ELEC 6200, Fall 07, Oct 24 10Jiang: Async. Processor Example: AMULET1

11. ELEC 6200, Fall 07, Oct 24 11Jiang: Async. Processor Example: Asynchronous DLX

12. ELEC 6200, Fall 07, Oct 24 12Jiang: Async. Processor Conclusion Asynchronous design is Asynchronous design is competitive with the best synchronous design in power efficiency and is close in performance and silicon area References References SCALP: A Superscalar Asynchronous Low-Power Processor, Philip Brian Endecott, Ph.D thesis of University of Manchester, UK, 1996 SCALP: A Superscalar Asynchronous Low-Power Processor, Philip Brian Endecott, Ph.D thesis of University of Manchester, UK, 1996 AMULET1: An Asynchronous ARM Microprocessor, J. V. Woods et al, IEEE Trans. on Computers, Vol.46.4, p.385-398, Apr 1997 AMULET1: An Asynchronous ARM Microprocessor, J. V. Woods et al, IEEE Trans. on Computers, Vol.46.4, p.385-398, Apr 1997 Automating the Design of an Asynchronous DLX Microprocessor, Manish Amde et al, DAC’03, p.502-507, June 2003 Automating the Design of an Asynchronous DLX Microprocessor, Manish Amde et al, DAC’03, p.502-507, June 2003