1. Paper review: High Speed Dynamic Asynchronous Pipeline: Self Precharging Style Name : Chi-Chuan Chuang Date : 2013/03/20

2. Outline Introduction Dual-rail asynchronous pipelines – PS0 pipeline – Lookahead pipelines Self precharging pipeline Timing constraints Simulation results Conclusion Advices

3. Introduction Asynchronous circuit’s functional blocks communicate with handshake protocol Asynchronous pipeline’s advantages – No global clock distribution problem – No clock skew – Lower power consumption – Automatically adapt to the environments

4. Introduction (cont.) Asynchronous pipelines have two types – Single-rail topology – Dual-rail topology Single-rail topology – Less area and wiring load – But always takes the worst case delay and additional timing margins Dual-rail topology – More robust data depended completion detection – Low throughput

5. Dual-rail asynchronous pipelines Williams’ PS0 pipeline Lookahead pipelines – LP3/1 pipeline – LP2/2 pipeline – LP2/1 pipeline Enhanced lookahead pipelines – Enhanced LP3/1 pipeline – Enhanced LP2/1 pipeline

6. Dual-rail asynchronous pipelines (cont.)

7. PS0 pipeline precharge

8. LP3/1 pipeline precharge

9. LP2/2 pipeline precharge

10. Asymmetric C element (aC)

11. LP2/1 pipeline precharge

12. Enhanced lookahead pipelines LP3/1 and LP2/1 pipelines have the problem of higher wiring load and larger number of inter-stage control signals It is difficult to communicate with the environments Enhanced lookahead pipelines reduce wire load but increase the cycle time

13. Enhanced LP3/1 pipeline precharge

14. Enhanced LP2/1 pipeline precharge

15. Comparison Reduce interstage control signal Communicate with environment

16. Self precharging pipeline Has all properties of a dual rail pipeline Each pipeline stage consists of – A functional block with domino gates – A completion detector – An special asymmetric C-element The completion detectors are moved just after the previous functional block – interstage wiring load is reduced

17. Self precharging pipeline (cont.) Completion detector’s done signal is used to precharge both the special aC and the functional block, called self precharging

18. Special asymmetric C element This completion detector has lesser area, delay and power consumption

19. Special asymmetric C element (cont.) Has two inputs coming from the CDs of current stage N and next stage (N+1) It’s functionality – When N+1 is 1 => output is 1 – When N+1 is 0 and N is 1 => output is 0 – Hold the previous value otherwise

20. Self precharging pipeline (cont.) precharge

21. Timing constraints

22. Simulation results Layout in 90nm UMC process, at 1.2V supply, temperature is 300K, normal process corner

23. Simulation results (cont.) Power and area – Enhanced LP3/1 has the highest power consumption and area, followed by PS0 – LP2/2 has the lowest power consumption and area – Enhanced LP2/1 and SP have almost same area and power consumption (but SP slightly higher)

24. Conclusion Self precharging protocol CDs are just placed after the previous stage aC removes the self takeover timing constraint of the LP family, makes it simpler to design High throughput (2.227G data items/s) Area and power consumption are comparable with LP2/1 pipeline low latency, high robustness, low power, avoidance of explicit latches etc. compared with synchronous counter parts

25. Comments

26. Thanks for your attention