STAR Pixel Detector Latch-up in Phase-1, SUZE and Mimosa22 Tests and analysis by Michal Szelezniak

LBNL-IPHC 06/ LG2 Talk Outline LU & SEU testing goals. SEU facility at BNL and test setup. LU cross-section for sensors measured. SEU. Observations and comments

33 Testing goals LBNL-IPHC 06/ LG Measure Latch-up cross-section in Phase-1 and SUZE. Measure Single Event Upsets in Phase-1 (Optional) Measure Latch-up and possible Single Event Upsets in Mimosa-22 We scheduled testing time at the BNL Tandem SEU test facility to do latch-up testing on May 14-15, 2009

44 Facility at BNL and Test setup LBNL-IPHC 06/ LG

55 Facility at BNL and Test setup LBNL-IPHC 06/ LG LU test program is a VI in Labview running on the PC The VI uses the NI digital IO interface to count latch-up events and reset the power to the DUT. The RDO board provides a firmware based JTAG refresh looking for SEU errors.

66 Facility at BNL and Test setup LBNL-IPHC 06/ LG Hardware used for the latch-up and SEU testing is the existing current RDO system Mass termination board with 4 LU protected power supply daughter-cards. These cards will detect latch-up and remove supply power both in this latch-up test run and in the real Pixel detector system.

77 Latch-up measurements Initial raw data sent to IPHC LBNL-IPHC 06/ LG 0-16F-19 Si-28 Cl-35 Ni-58 Br-81 I-127 Au-197

88 Latch-up measurements Final (corrected) LBNL-IPHC 06/ LG

99 Latch-up measurements Mimosa-22 LBNL-IPHC 06/ LG Mimosa22:

10 Latch-up measurements Phase-1 LBNL-IPHC 06/ LG

11 Latch-up comments All latch-up detected in SUZE occurred on the VDD- FIFO supply line. The lowest cross-section values for Phase-1, SUZE, and M22 are calculated with a single registered latch up occurrence. The corrected LU cross-section plots have removed data that had latch-ups occurring at the reset frequency of the testing system. LBNL-IPHC 06/ LG

12 LBNL-IPHC 06/ LG SEU analysis (first look) PRELIMINARY First look at Phase-1 data shows similar results (single corrupted bits may be possible at LET values slightly lower than for the first latch up events) Goals of SEU analysis Measure onset of errors (first look at the collected data shows that it is in the LET range for latch up events) Check for the likelihood of corruptions 0  1 and 1  0 Check if bit corruptions are equally likely in different registers and at different positions in registers No errors and no latch up More result to come…

13 Observations and comments All 3 prototypes are more susceptible to latch up than Mimostar-2. SUZE is more susceptible to latch up by a factor of ~5. In general, we are not expecting to see these levels of LET during normal running conditions at STAR. Possible exceptions would be unusual events such as beam dumps and during beam injection. We will complete the SEU analysis and report. LBNL-IPHC 06/ LG

14 end LBNL-IPHC 06/ LG