Las Palmas de G.C., Dec. 1999 IUMA Projects and activities.

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Presentation transcript:

Las Palmas de G.C., Dec IUMA Projects and activities

Las Palmas de G.C., Dec Examples of projects ä Creation of a ciphering engine using RISC and cryptographic circuits for ISDN applications ä Implemention of a VIS in SPARC V.8 for cheap multimedia applications ä High-level synthesis system for DSP circuits ä Implementation of electronic systems in MCM with Cadence/Allegro ä Algorithms for multimedia in the MVP (TMS320C80) development system. ä...

Las Palmas de G.C., Dec JavaRISC Project ä Hardware implementation of the JAVA Virtual Machine usign RISC style architecture ä Synthetized from a RT Level VHDL description using Synopsys and Cadence  Implemented in CMOS ES2 0.7  m technology

Las Palmas de G.C., Dec T-DES Project ä Interchip Digital Link Interface for direct connection to ISDN ä Triple DES Cipher Algorithm ä Synthetized from VHDL using Synopsys and Cadence  Results for ES2 CMOS 0.7  m: ä gates ä transistors ä 15.6 mm 2 ä Peak throughput: 256 kbps

Las Palmas de G.C., Dec CEIP Project: Cipher Engine for ISDN ä Includes: ä 2 Flash-RAM Chips ä 4 Static RAM ä 1 microcontroller RISC ä 15 T-DES CFB Chips ä 1 ASIC

Las Palmas de G.C., Dec ATM project ATM Physical Layer Trans conductance amp Clock recovery Cell delineation Error recovery HEC generation ATM Layer VPI label trans- lation Policing Routing label RX/TXLaserdiode SRAM CPU Photodiode Micro machined alignment H-GaAs-IV Multi Chip module C-GaAsH-GaAs-IV Switchfabric Operations and management

Las Palmas de G.C., Dec ATM Project (FIFO)

Las Palmas de G.C., Dec ATM Project (test bench)

Las Palmas de G.C., Dec ATM Project (test bench)

Las Palmas de G.C., Dec Fast Fourier Transform Project ä Processing unit  process every butterfly ä Routing unit Routing unit. Processing unit

Las Palmas de G.C., Dec Fast Fourier Transform Project ä Processing Unit +  W N m  - + a b a´ b´

Las Palmas de G.C., Dec Fast Fourier Transform Project 1. Initial stage 2. Scale factor 3. radix2/radix4 combination 4.  i coefficients stored in a ROM 5. Post-processing 6. Vector Merging Adder 7. Control Unit

Las Palmas de G.C., Dec Fast Fourier Transform Project ä Convergence and scale factor for N=16 and  =  /3 Escale factor Convergence radix2radix4repeatscal. zizi

Las Palmas de G.C., Dec Fast Fourier Transfor Project (results) Delays and power dissipation FFT Processor characteristics Power = 12,5 W Area = 5732 x 6070  m 2 (35 mm 2 ) Encapsulated = LD256

Las Palmas de G.C., Dec Fast Fourier Transfor Project (results) ä Comparison with other architectures

Las Palmas de G.C., Dec The Crosspoint Switch has 32 data inputs and 32 data outputs. Any input can be multiplexed to any, some or all outputs. Signals in data path are fully differential to minimize duty cycle distortion and achieve an excepcional signal fidelity.  VSC851 Project The switch is configured by sequentially loading each multiplexer’s 5-bit Holding register with the desired input address D[4:0]. When complete, a high pulse is applied to GSTROBE and all new configurations are simultaneously transferred into the switch multiplexers.

Las Palmas de G.C., Dec VSC851 Project Switch Matrix Control Logic

Las Palmas de G.C., Dec VSC851 Project

Las Palmas de G.C., Dec VSC851 Project (testing procedure)  Propagation Delay. Duty Cycle Distortion. Output Skew. Minimum Input Pulse Width. Maximum Bit Rate. Jitter & Interchannel Coupling. In order to test the 1.6 Gb/s 32x32 Crosspoint Switch, a characterization board was designed. This board allows to measure the following parameters:

Las Palmas de G.C., Dec VSC851 Project (testing procedure)

Las Palmas de G.C., Dec VSC851 Project (testing results) Four boards with chips from different lots were tested. According with the test, the Crosspoint Switch is fully with a 90% of nominal differential amplitude. 

Las Palmas de G.C., Dec VSC851 Project (comparative results)

Las Palmas de G.C., Dec VSC851 Project ä Power consumption: 9 W ä Duty cycle distortion < 150 ps ä 1 st case: 5  s to “0” and = 265 ps on “1”, 142 on “0” ä 2nd case: and ä Propagation delay = 1,8 ns ä Output to output skew < 300 ps ä Minimum pulse width = 720 ps ä Packaging = 256-pin LDCC ä Power supply: -2V y 3,3 V ä Output level: 3,3 V TTL y ECL differential

Las Palmas de G.C., Dec OLYMPO Project

Las Palmas de G.C., Dec Summary ä Research and development projects funded by European Union, Spanish government, Canary government and industries. ä CMOS, GaAs and SiGe technology based. ä Projects for digital processing, communications, computers, CAD tools... ä Around 20 researchers involved in these projects.