1. Conception d’un processeur DSP faible énergie en logique ternaire
O. SENTIEYS, M. ALINE, E. KINVI-BOH
Université de Rennes - ENSSAT
IRISA
FTFC 2003, Paris, Mai 2003

2. Outline Motivations MVL implementation with SUS-LOC
Principle of SUS-LOC structures
Characterization at the transistor-level
Characterization at the gate-level
Design of a ternary DSP structure
Experimental results and comparisons
Conclusion and future works

3. Multiple Valued Logic (MVL)
Currently, computers and other electronic devices run as … binary logic with 2 logical states: 0, 1
MVL can offer:
Many logical states: 0, 1, 2, 3, …
More complex functions
in less time, power and area than binary ?
MVL circuit structure ?
Until the SUS-LOC circuit structure was developed, MVL was impractical or unachievable through conventional means, and drew only theoreticians and researchers looking for the key to making it usable

4. MVL Circuits Structures
Current-Mode CMOS Logic (CMCL) [3]
Voltage-Mode nMOS technology [16]
QCD or CCD technology [1][2]
Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) [8][11]
Voltage-Mode (i.e. CMOS)
Energy Efficient
A new promising structure

5. Technical advantages of SUS-LOC MVL circuits and devices
An increase in data density
Interconnections
e.g. 40 bits become 25 terts1 (37.5% reduction), or 20 4L-digits
More bandwidth with a reduced clock rate
16 bits f 10 terts
1 Mbit/s  750 ktert/s
Reduced package size
A decrease of passive parasitic values
A decrease in required power (dynamic and static)
Ability to perform multiple logic functions in one operation
e.g. (A+B) AND D
Security, confidentiality
1 terts stands for ternary digits

6. SUS-LOC structures Principle Ternary case: radix r = 3
SUS-LOC principle
SUS-LOC structures
Transistor library
Characterization
Process
Principle
Ternary case: radix r = 3
Logic states: {0,1,2}
r-1 different sources of power
e.g. {0V, 1.25V, 2.5V}
r-1 independent controllable paths
VHDL Performance
modeling
Output V0 V1 V2
Inputs N0 N1 N2

7. SUS-LOC structures Example: ternary inverter Truth Table
SUS-LOC principle
SUS-LOC structures
Transistor library
Characterization
Process
Example: ternary inverter
Truth Table
N(x) = <2 1 0>
VHDL Performance
modeling 2 1 2 X S F 1 2

8. Transistor Library Use of depleted and enhanced MOS transistors
SUS-LOC principle
Transistor Library
Transistor library
Characterization
Process
Use of depleted and enhanced MOS transistors
SPICE models
0.25m technolgy
2m SOI technolgy (UCL)
VHDL Performance
modeling
Id(Vgs)
MbreakPD
MbreakND
MbreakP
MbreakN
MbreakP+
MbreakN+

9. Logic Functions Ternary CGAND Complementing Generalized AND
SUS-LOC principle
Logic Functions
Transistor library
Characterization
Process
Ternary CGAND
Complementing Generalized AND
CGAND(X,Y) = N(MAX(x,y))
VHDL Performance
modeling A B S
CGAND3

10. CGAND

11. CGAND

12. Characterization Transistor-level Validation
SUS-LOC principle
Characterization
Transistor library
Characterization
Process
Transistor-level Validation
Delay and Power Characterization
VHDL Performance
modeling
XCIRCUIT
MVLStim
ELDO
Hierarchical
netlist
MVLCara
Report
file

13. Characterization Transistor-level Validation
SUS-LOC principle
Characterization
Transistor library
Characterization
Process
Transistor-level Validation
Delay and Power Characterization
e.g. Ternary vs Binary Inverter
VHDL Performance
modeling

14. Design of a ternary standard cell library
CGAND, CGOR, Inverters, …
Mux, Tri-state
LATCH, D Flip-Flop
SRAM memory cell and sense amp.
Arithmetic components
HA, Pi, Gi, CLA, multiplier
1T-Shifter

15. Gate-level VHDL package for simulation
SUS-LOC principle
Gate-level
Transistor library
Characterization
Process
VHDL package for simulation
STD_TERNARY_LOGIC
VHDL set of tools for architecture- and gate-level estimations
Power, Delay
Gate-level simulation
VHDL Performance
modeling
ELDO simulation
Report file
VHDL Package
VHDL Gate level
simulation
Power consumption
Delay
Description.vhd

16. Outline Motivations MVL implementation with SUS-LOC
Design of a ternary DSP structure
Experimental results and comparisons
Conclusion and future works

17. A ternary vs. binary DSP Barrel shifter ALU Multiplier Adder
T register DB
MUX
Multiplier
Adder
A(H)
B(H)
ALU
Barrel shifter
Legend :
A Accumulator A
B Accumulator B
C CB data bus
D DB data bus
E EB data bus
M MAC unit
S Barrel shifter
T T register
U ALU T D A C B M U S CB EB L N H E
Bus width :
L : 16 bits, 10 terts
N : 32 bits, 20 terts
H : 40 bits, 25 terts

18. Interconnections Bus structure Activity of wires
16 bits become 10 terts
40 bits become 25 terts
Activity of wires
Binary:
Ternary:

19. SRAM Memory Transistor equivalent, faster access time
Up to 50% in energy reduction

20. SRAM Memory

21. Arithmetic structures
e.g. 40-bit vs. 25-tert Sklansky Adder
100 vs. 54 Brent and Kung cells 
Computation of the pair of terts (Gi, Pi)
Sum tert computation Si = Ai + Bi + Ci-1
C25 A 25 B S

22. Arithmetic structures
e.g. 40-bit vs. 25-tert Sklansky Adder
100 vs. 54 Brent and Kung cells

23. Other Structures

24. Conclusion and future works
SUS-LOC concepts for a ternary DSP
Experiments on representative modules
Comparison: SUS-LOC vs. CMOS circuits
High energy efficiency
Future works
Prototype chip with an SOI technology
3L and 4L SRAM and Flash memories
Optimization of arithmetic structures …

25. Test Vectors Schematic Netlist Characterization Results Process
Power, Delay Time
Simulation
VHDL (Synopsys)

26. Id = F(Vgs) Id Vgs Vtp V'tn V'tp Vtn MBREAK P MBREAK PD MBREAK ND
V'tp
Vtn

27. CGAND

28. SUS-LOC structures List of some designed cells
Inverter function N(x)=<210>
C0=<200>, C1=<020>, C2=<002>
CGOR(x,y)=N(MAX(x,y))
2-input multiplier M(x,y)=x*y
M(x,y)=x*y
M’(x,y, Cin)=(x*y)+Cin
Ternary half-adder
THA(x,y,Cin)=x+y+Cin
2- or 3-input multiplexers
Optimized adders structures
Ternary SRAM