Engineering 4862 Microprocessors Lecture 22 Cheng Li EN-4012

Engr 4862 Microprocessors 8088 / 8086 CPU in Min Mode

Engr 4862 Microprocessors 8086/88 uPro and Supporting Chips –Pin descriptions for 8086/88 BHE (Active Low, Bus High Enable): Pin 34 –Used to distinguish between the low byte and the high byte of the data for the 16-bit external data bus of 8086 –Together with A0 BHEA bitD0-D bitUpper half, D8-D bitLower half, D0-D7 11Data Bus Idle NMI (Non-Maskable Interrupt) –An rising edge-triggered input signal to the processor READY –Low level-active signal, insert a WAIT state

Engr 4862 Microprocessors 8086/88 uPro and Supporting Chips –Pin descriptions for 8086/88 INTR (Interrupt Request) –An active-high level-triggered input signal to the processor –Sampled in the last clock cycle of each instruction –In IBM PC, this is connected to the 8259 Interrupt controller Clock (heart beat of CPU) –Need to be accurate for event synchronization and driving CPU –An input signal and is connected to 8284 clock generator RESET –Active high signal came from 8284 –Force the uPros to stop any activities and to discard everything –Data after reset: CS: FFFFH, IP: 0000H, DS ES SS: 0000H Flags: Cleared, Queue: Empty

Engr 4862 Microprocessors Min / Max Mode (Pin 24–31) –Minimum mode Pin #33 (MN/MX) connect to +5V Pin are used as memory and I/O control signal The control signals are generated internally by the 8086/88 More cost-efficient –Maximum mode Pin #33 (MN/MX) connect to Ground Some control signals are generated externally by the 8288 bus controller chip Max mode is used when math processor is used.

Engr 4862 Microprocessors Control Signal Generation in Min Mode

Engr 4862 Microprocessors Three Buses in 8088 Based System

Engr 4862 Microprocessors Min / Max Mode (Pin 24–31) –Maximum mode S 2, S 1, S 0 connect directly to INTAInterrupt Acknowledgment IORCRead I/O Port IOWCWrite I/O Port NONEHalt MRDCCode Access MRDCRead Memory MWTCWrite Memory PassiveNone

Engr 4862 Microprocessors 8086/8088 in Max Mode

Engr 4862 Microprocessors 8288 Bus Controller

Engr 4862 Microprocessors The Clock The clock signal is very important to the operation of a microprocessor circuit. It synchronizes the sequential activities of the CPU and the system –Not all devices use a clock signal (eg. PPI)

Engr 4862 Microprocessors 8284 Clock Generator and Driver The 8088/8086 CPUs require a specific waveform for the system clock –Fast rise and fall times ( <10ns ) –Logic 0: -0.5 to 0.6 V –Logic 1: 3.9 to 5.0 V –Duty cycle of 33%

Engr 4862 Microprocessors 8284 Clock Generator and Driver 33% Duty Cycle

Engr 4862 Microprocessors 8284 Clock Generator

Engr 4862 Microprocessors 8284 Clock Generator and Driver The 8284 provides the proper clock signal –Uses a crystal oscillator (3 oscillations per clock) Provides the correct waveforms for other signals to CPU –RESET –Request for wait state

Engr 4862 Microprocessors 8284 Clock Generator and Driver –An 18-pin chip. Not only provide the clock and synchronization for the microprocessor, but also provides the READY signal for the insertion of WAIT states into the CPU bus cycle. –Input Pins RES (Reset In): from power supplier X1 and X2 (Crystal In): the crystal frequency must be 3 times the desired frequency for the microprocessor –For IBM PC, MHz (max 24 MHz) RDY1 and AEN1: provide a Ready signal to the mPro, which will insert a WAIT state to the CPU read/write cycle. RDY2 and AEN2: For multiprocessor systems

Engr 4862 Microprocessors 8284 Clock Generator and Driver –Output Signals RESET: reset signal to the 8086/88, activated by RES OSC (oscillator): provide to the expansion slot CLK (clock): 1/3 of the OSC or EFI input, with a duty cycle of 33% –In IBM PC, OSC = MHz, so CLK = MHz PCLK: one-half of CLK (1/6 of crystal) with duty cycle of 50% and is TTL compatible. Provide to 8253 Timer to generate speaker tones READY: connect to READY input of CPU to insert WAIT state

Engr 4862 Microprocessors Other Supporting Chips –8288 Bus Controller A 20-pin chip to provide all the control signals when the 8086/88 is in the maximum mode –74LS373 Latch Provide isolation and bus boosting –74LS244 Unidirectional data transceiver chip –74LS245 Bidirectional data transceiver chip Provide bus buffering and boosting

Engr 4862 Microprocessors Machine Cycles Also Bus Cycles Definition: –One discrete information transfer on the buses. This includes the address, data, and control information.

Engr 4862 Microprocessors Machine Cycles A machine (bus) cycle consists of at least four clock cycles, called T states. A specific, defined action occurs during each T state (labeled T1 – T4) –T1: Address is output –T2: Bus cycle type (Mem/IO, read/write) –T3: Data is supplied –T4: Data latched by CPU, control signals removed

Engr 4862 Microprocessors By memory or I/O device By microprocessor

Engr 4862 Microprocessors T States Why are there T states? –In the 8086/8088, the address and data lines are multiplexed. –The microprocessor needs time to change the signals during each bus cycle. –Memory devices need time to decipher the address value and then read/write the data (access time)

Engr 4862 Microprocessors Timing The period of one bus cycle is at least four times a clock cycle –10-MHz 8086 CPU –Each clock cycle has a period of 100ns –Machine cycle period is 400ns

Engr 4862 Microprocessors Timing 100 ns 400 ns

Engr 4862 Microprocessors Timing Although the system clock has a constant period, the bus cycle does not –Slow devices (memory or I/O) must request extra time. –The microprocessor inserts extra wait states between states T3 and T4 The alternatives are to slow down the system clock, or use faster devices

Engr 4862 Microprocessors Timing Wait state inserted here

Engr 4862 Microprocessors I/O Design When designing an I/O port, ensure that the port is only active when selected by the microprocessor –Use latches (output) and buffers (input) to isolate the I/O port circuitry from the address and data bus –Use the correct combinatorial logic circuitry and/or decoders with address bus to select the port

Engr 4862 Microprocessors Input / Output Instructions For 8-bit port IN AL, Port #OUT Port #, ALMOV DX, Port # IN AL, DXOUT DX, AL For 16-bit port IN AX, Port #OUT Port #, AXMOV DX, Port # IN AX, DXOUT DX, AX

Engr 4862 Microprocessors Input / Output Instructions Since 8086/88 has a 16-bit data bus internally, it is capable of transferring 16-bit data to or from AX.  This requires having two port addresses, one for each byte! Example: AX = 9876H, Port # = 40H OUT 40H, AX  Port 40  76H (AL), Port 41  98H(AH) For 8086, takes one bus cycle to complete the transfer, for 8088, two bus cycles are required

Engr 4862 Microprocessors Output Design Example: 8 LEDs This is a byte-wide output port The LEDs cannot be connected directly to data bus –Difficult to select the LEDs –LEDs would only display value for very short period of time (about 400ns, or 2 clock cycles) Only when data bus carries the correct signal –Microprocessor cannot sink enough current

Engr 4862 Microprocessors Example: 8 LEDs Instead, we need to capture the values on the data bus, and hold them until changed –The 74LS373 octal latch will do nicely LS373 Data bus

Engr 4862 Microprocessors Example: 8 LEDs We only want the latch to load values from the data bus when the microprocessor outputs to the correct port # –Suggestion 1: Decode the address directly –Suggestion 2: Use a decoder such as the 3x8 74LS138 with lines from the address bus

Engr 4862 Microprocessors Example: 8 LEDs DQ D0 74LS373 D7 Q0 Q7 System Data Bus Latch Out OC System Address Bus IOW G

Engr 4862 Microprocessors Example: 8 LEDs LS373 Data bus 74LS138 Address bus Note: This is not quite enough!

Engr 4862 Microprocessors Example: 8 LEDs How do we connect the LEDs? –2 possibilities

Engr 4862 Microprocessors Example: 8 LEDs LS V

Engr 4862 Microprocessors Example: 8 LEDs LS V The 74LS373 does not have enough power to drive an LED. The device can sink enough current for the LED to light (15 to 20 mA). 180ohms

Engr 4862 Microprocessors Bus Cycles for outputting Assume the port address is 99H  OUT 99H, AL –T1: address 99H is provided to address bus A0 – A7 through AD0 – AD7 and ALE signal –T2: IOW is provided and the contents of AL are released into the data bus pins AD0 – AD7 –T3: signal propagates to the destination port –T4: the content of AL are latched into the 74LS373 with the IOW going from low to high

Engr 4862 Microprocessors Example: 8 Switches Now we will look at an 8-bit input port. The procedure to select the port is similar to the output case –Use IORD* instead of IOWR*

Engr 4862 Microprocessors Example: 8 Switches We cannot use a latch to separate the switches from the microprocessor –We only want the switch values to be on the data bus when the microprocessor asks for it –A latch would constantly drive the bus!

Engr 4862 Microprocessors Example: 8 Switches The device of interest here is the 74LS244 tristate buffer (unidirectional) –NOT the same as the 74LS245 transceiver (bidirectional) Tristate: –One of three states: on (1), off (0), or open (Z) –In the open state, the buffer does not drive the data bus

Engr 4862 Microprocessors Example: 8 Switches How do we set up the switches? –When open, one logic level –When closed, the other logic level

Engr 4862 Microprocessors Example: 8 Switches LS V 10K ohms

Engr 4862 Microprocessors Example: 8 Switches D0 74LS244 D7 Q0 Q7 Switches To System Data Bus G1 System Address Bus IOR D4 G2

Engr 4862 Microprocessors Summary Since the data provided by the CPU to the port is on the system data bus for a limited amount of time ( ns), it must be latched before it is lost In order to prevent any unwanted data from coming into the system data bus, all input devices must isolated through the tri-state buffer –The 74LS244 not only plays this role, but also provides the incoming signals sufficient strength (boosting) to travel all the ways to the CPU. As general, every device (memory, peripherals) connected to the global data bus must have a latch ot tri- state buffer

Engr 4862 Microprocessors Programmable I/O The previous examples are good for many applications, but sometimes a more powerful and flexible solution is needed. The 8255 Programmable Peripheral Interface (PPI) is a 40-pin DIP IC that provides 3 programmable I/O ports, A, B, and C. One can program the individual port to be input or output port, economical and flexible than 74LS373, 73LS244, which must be hard wired)

Engr 4862 Microprocessors Programmable I/O How are is it programmable? –Configure each port as input or output –Different modes of operation You must initialize the PPI via software commands –Send a control byte to the device’s control register port

Engr 4862 Microprocessors Pin Description PA0 – PA7: Port A / All / input/output/bidirectional PB0 – PB7: Port B / All / input/output PC0 – PC7: Port C / All / input/output Can be split into two parts: Upper (PC7 – PC4) and Lower (PC3 – PC0). Each can be used for input or output. Any of PC0 – PC7 can be programmed. RD and WR: control signal input to 8255 IOR and IOW in peripheral I/O MEMR and MEMW in memory-mapped I/O

Engr 4862 Microprocessors Pin Description RESET: Active high input signal to 8255 –Used to clear the internal control register –When activated, all ports are initialized as input ports. –Usually connect to the RESET output of the system bus or ground A0, A1, and CS –CS selects the entire chip, A0 and A1 select the specified port –Used to access port A, B, C, CS A1 A0 Select or control register Port A Port B Port C Control Reg. 1 x x Not Selected

Engr 4862 Microprocessors Control Word of 8255 Port C Lower PC 3 -PC 0 1 = input, 0 = output Port B 1 = input, 0 = output Mode Selection 0 = Mode0, 1 = Mode1 Port C Upper PC 7 -PC 4 1 = input, 0 = output Port A 1 = input, 0 = output Mode Selection 00 = Mode0, 01 = Mode1 1x = Mode 2 1 = I / O Mode 0 = BSR Mode Group B Group A D7D7 D6D6 D3D3 D2D2 D1D1 D0D0 D5D5 D4D4

Engr 4862 Microprocessors Mode Selection It’s the control register that must be programmed to select the operation mode of the three ports: A, B, and C The 8255 chip is programmed in any of the above modes by sending a byte (control word) to the control register of the 8255

Engr 4862 Microprocessors Mode Selection Mode 0: simple I/O –Any ports: A, B, CL, CU. No control of individual bits Mode 1: I/O (ports A and B) with handshaking (port C) –Synchronizes communication between an intelligent device (printer) Mode 2: Bi-directional I/O with handshaking –Port A: bidirectional I/O with handshaking through port C –Port B: Simple I/O or in handshake mode 1 BSR Mode: Bit set/reset –Only the individual bits on Port C can be programmed

Engr 4862 Microprocessors 8255 Design Example D0 D7 A2 System Address Bus IOW A7 D0 D7 IOR WR RD A0 A1 A0 A1 CS A B CL CH

Engr 4862 Microprocessors 8255 Design Example Mode 0 –Any of ports A, B, C can be programmed as input or output –Port can not be both an input and output port at the same time –Port C can be programmed with CL, CH separately –Example: