CS370 – Spring 2003 Programmable Logic Devices PALs/PLAs

Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form PALs and PLAs

Example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A Equations Key to Success: Shared Product Terms 1 = asserted in term 0 = negated in term - = does not participate 1 = term connected to output 0 = no connection to output Input Side: Output Side: PALs and PLAs

Example Continued All possible connections are available before programming

PALs and PLAs Example Continued Note: some array structures work by making connections rather than breaking them

Alternative representation for high fan-in structures Short-hand notation so that all the wires need not be drawn! Notation for implementing F0 = A B + A' B' F1 = C D' + C' D PALs and PLAs AB CD A BC D AB +CD +

PALs and PLAs ABC A B C A B C F1F2F3F4F5F6 Design Example F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A xor B xor C F6 = A xnor B xnor C Multiple functions of A, B, C A BC

Difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA): PAL concept -- implemented by Monolithic Memories constrained topology of the OR Array – I.e., the OR array cannot be fully programmed. A given column of the OR array has access to only a subset of the possible product terms PLA concept generalized topologies in AND and OR planes PALs and PLAs

Design Example: BCD to Gray Code Converter Truth Table K-maps W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' Minimized Functions: PALs and PLAs

Programmed PAL: 4 product terms per each OR gate

Code Converter Discrete Gate Implementation 4 SSI Packages vs. 1 PLA/PAL Package! PALs and PLAs

Example: Magnitude Comparator EQNELTGT ABCD AC BD ABD BCD ABC BCD PALs and PLAs A B C D