ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.

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Presentation transcript:

ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran

Stepwise refinement At each level of abstraction, we must: analyze the design to determine characteristics of the current state of the design; refine the design to add detail. Design: specify and enter the design intent Verify: verify the correctness of design and implementation Implement: refine the design through all phases ECOE 560, Spring 2004

Successive refinement model specify specify architect architect design design build build test test initial system refined system ECOE 560, Spring 2004

Hardware/software design flow requirements and specification architecture software design hardware design integration testing ECOE 560, Spring 2004

Hierarchical HW/SW flow spec architecture HW SW integrate test system spec HW architecture detailed design integration test hardware spec SW architecture detailed design integration test software ECOE 560, Spring 2004

ECOE 560, Spring 2004

ECOE 560, Spring 2004

Outline of today’s lecture What is a software/hardware (embedded) system? Course outline Design automation methodologies and tools Levels of abstraction in design descriptions ECOE 560, Spring 2004

Levels of Abstraction: Hardware System level Register-transfer level (RTL) Gate level Transistor level Layout level ECOE 560, Spring 2004

ECOE 560, Spring 2004

ECOE 560, Spring 2004

ECOE 560, Spring 2004

ECOE 560, Spring 2004

ECOE 560, Spring 2004

Levels of Abstraction: Software Specification: Behavioral (UML diagrams, statecharts, algorithm pseudocode) Architecture: Structural (UML), SystemC Implementation: High-level language Assembly Executable (binary) ECOE 560, Spring 2004

Data flow graph a b c d + - y x * + z y1 DFG x = a + b; y = c - d; z = x * y; y1 = b + d; single assignment form a b c d + - y x * + z y1 DFG

Control-data flow graph CDFG: represents control and data. Uses data flow graphs as components. Two types of nodes: decision; data flow.

CDFG example T cond1 bb1() F bb2() bb3() test1 c3 c1 c2 bb4() bb5() if (cond1) bb1(); else bb2(); bb3(); switch (test1) { case c1: bb4(); break; case c2: bb5(); break; case c3: bb6(); break; } T cond1 bb1() F bb2() bb3() test1 c3 c1 c2 bb4() bb5() bb6()

Course Outline System design flow Modeling, specifying, and representing systems: Description languages for design specifications and implementations Modeling formalisms: Models of computation and concurrency Fundamentals: Boolean algebras, functions, relations. Propositional logic, first-order logic. Temporal logics. Hardware implementation (component) technologies: CPUs, ASICs, FPGAs, DSPs, IP blocks, I/O components, networks, buses, on-chip communication networks, reconfigurable platforms. Software implementation (component) technologies: Operating systems, real-time operating systems, inter-process communication, scheduling. Analysis, verification, testing: Functionality. Design and implementation verification. Simulation, emulation, formal verification. Analysis, verification, testing: Performance and timing. Timing analysis and verification of hardware and software. Performance evaluation and estimation. Analysis, verification, testing: Power. Power analysis, optimization of hardware and software. Power minimization techniques. System partitioning, architecture exploration. Hardware synthesis. Software synthesis Interface design and synthesis ECOE 560, Spring 2004