THE INTERCONNECT

The Wire schematics physical

Interconnect Impact on Chip

Wire Models Capacitance-only All-inclusive model

Impact of Interconnect Parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive

Nature of Interconnect Global Interconnect S Global = S Die S Local = S Technology Source: Intel

Nature of Interconnect

INTERCONNECT

Capacitance of Wire Interconnect

Capacitance: The Parallel Plate Model

Permittivity

Fringing Capacitance

Fringing versus Parallel Plate

Inter-wire Capacitance (1)

Interwire Capacitance (2)

Impact of Interwire Capacitance

Wiring Capacitances (0.25 mm CMOS)

Inter-Wiring Capacitances (0.25 mm CMOS)

INTERCONNECT

Wire Resistance r L R = H W Sheet Resistance L R H R R 1 2 W

Interconnect Resistance

Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers

Polycide Gate MOSFET Silicides: WSi TiSi , PtSi and TaSi PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2 , PtSi and TaSi Conductivity: 8-10 times better than Poly

Sheet Resistance

Modern Interconnect

Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

INTERCONNECT Dealing with Inductance

Wire Inductance L H W

INTERCONNECT Interconnect Modeling

Modeling Wires Lumped Capacitance Model Lumped Resistance Lumped Inductance Distributed & Lumped RC Model Transmission Line Model

Small Interconnect Resistance assumed The Lumped Model Clumoed = L x cwire Small Interconnect Resistance assumed 50 % t = ln(2)t = 0.69t 90 % t = ln(9)t = 2.2t

Lumped Resistance/Inductance Useful for Supply line Modeling Parasitic Resistance causes supply voltage drop. Parasitic Inductance causes bouncing on supply rail.

The Lumped RC-Model The Elmore Delay

The Ellmore Delay RC Chain

Wire Model Assume: Wire modeled by N equal-length segments For large values of N:

The Distributed RC-line R = L.r C=L.c t(Vout) = RC = rcL2 Diffusion Equation

Step-response of RC wire as a function of time and space

RC-Models

Driving an RC-line Condition for dominant wire

Design Rules of Thumb rc delays should only be considered when tpRC > tpgate of the driving gate Lcrit >  tpgate/0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line trise < 0.9 RC Lcrit >  trise/0.9rc when not met, the change in the signal is slower than the propagation delay of the wire For metal interconnect L = 3.2 mm in a 1.0 µm technology

Creating RC-Models for SPICE Only 3% Error

The Transmission Line Model

Lossless Transmission Line - Parameters Speed of light vacuum Relative permeability of insulator Relative permittivity of insulator

Wave Propagation Speed

Lossless Transmission Line - Model Characteristic Impedance 50 – 100 

Wave Reflection for Different Terminations Reflection Coefficient

Transmission Line Response

Transmission Line Response (RL= )

Lattice Diagram

When to Consider Transmission Line Effects? (1) Rule of Thumb For on-chip wires of up to 1 cm tr <150 psec For board wires of up to 50 cm tr <8 nsec

When to Consider Transmission Line Effects? (2) Otherwise distributed RC Model should be used Combining two conditions

When to Consider Transmission Line Effects Examples (1) Hard to achieve in Current technologies

When to Consider Transmission Line Effects Examples (2)

Loss Less Transmission Line Model for SPICE Approach One: Transmission Delay TD Approach Two: A Frequency F together with Normalized Electrical Length of the Transmission Line NL NL = F . TD