Oct 2013Sharif University of Technology1 Simple Half-rate phase detector detects but has no reference! Optical Communications: Circuits, Systems and Devices.

Slides:



Advertisements
Similar presentations
Microsoft PowerPoint 2007 Noris Bt. Ismail Faculty of Information and Communication Technology Tel : (Ext 8408)
Advertisements

Use of Nano Reactors in Edible Oil Processing
(C) National Institute of Information and Communications Technology1 AKARI Architecture Design Project for a New Generation Network Future Network Architectures.
Enterprise Transition to Lean Roadmap
14 Decembe 20101Institute for Aerospace Technology Professor Andrew Long Director – Institute for Aerospace Technology.
Acadia Institute for Teaching and Technology1 The more effectively we give and receive feedback, the more likely we are to promote learning - that of our.
Acadia Institute for Teaching and Technology1 Principles of good teaching practice.
Paolo Branchini, Salvatore Loffredo
A Stabilization Technique for Phase-Locked Frequency Synthesizers Tai-Cheng Lee and Behzad Razavi IEEE Journal of Solid-State Circuits, Vol. 38, June 2003.
Basic Finite State Machines 1. 2 Finite State Machines Binary encoded state machines –The number of flip-flops is the smallest number m such that 2 m.
Charge Pump PLL.
Requirement-Based Automated Aspect Verification Boris Vaysburg This presentation will probably involve audience discussion, which will create action items.
1 A latch is a pair of cross-coupled inverters –They can be NAND or NOR gates as shown –Consider their behavior (each step is one gate delay in time) –From.
Accreditation in Applied Science Computing, Engineering, and Technology Dr. Raymond Greenlaw Department of Computer Science Armstrong Atlantic State University.
WORD PROCESSOR MICROSOFT WORD BCOMP0101 Introduction to Information Technology Noris Bt. Ismail Faculty of Information and Communication Technology Tel.
Optical Fiber Communications Technology, Systems and Circuits Overview Lecturer: Ali Fotowat Ahmady Feb 7, 2012 Tabriz University Photonics Conference.
Synchronous Counters with SSI Gates
End of Column Circuits Sakari Tiuraniemi - CERN. EOC Architecture 45 9 Ref CLK 40 MHz DLL 32-bit TDC bank address RX 5 TDC bank address RX 5 TDC bank.
COMMUNICATION SYSTEM EEEB453 Chapter 3 (III) ANGLE MODULATION
MATLAB Applications By: Ramy Yousry.
Reconfigurable Computing - Clocks John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound, Western Australia.
 Phase detector:  Loop filter:  VCO: Phase Locked Loop (PLL) Design by Akin Akturk and Zeynep Dilli Figure 1: Basic PLL building blocks.
Oct 11, 2005CS477: Analog and Digital Communications1 FM Generation and Detection Analog and Digital Communications Autumn
Phase Difference = Phase Difference = 0.05.
What Happened Yesterday Steve Holt *ADC speed does not necessarily depend on clock speed; GHz crystal not needed Mihir Ravel *Voltage tolerance of the.
Laser Tracking System (LTS) Son Nguyen Jassim Alshamali Aja ArmstrongMatt Aamold.
Principles of Electronic Communication Systems
Electronic Counters.
Ayman Khattab Mohamed Saleh Mostafa El-Khouly Tarek El-Rifai
Sequential Logic - An Overview
Lecture 22: PLLs and DLLs. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 22: PLLs and DLLs2 Outline  Clock System Architecture  Phase-Locked Loops  Delay-Locked.
Motivation Yang You 1, Jinghong Chen 1, Datao Gong 2, Deping Huang 1, Tiankuan Liu 2, Jingbo Ye 2 1 Department of Electrical Engineering, Southern Methodist.
Special Topic-I PLL Basics and Design By, Anil Kumar Ram Rakhyani (akram)
TOF Electronics Qi An Fast Electronics Lab, USTC Sept. 16~17, 2002.
Computers Central Processor Unit. Basic Computer System MAIN MEMORY ALUCNTL..... BUS CONTROLLER Processor I/O moduleInterconnections BUS Memory.
Phase Detector Circuits
Slide: 1International Conference on Electronics, Circuits, and Systems 2010 Department of Electrical and Computer Engineering University of New Mexico.
111 Lecture 5 Basic Modulation Techniques (I) Principles of Communications Fall 2008 NCTU EE Tzu-Hsien Sang.
CHAPTER 15 Special ICs. Objectives Describe and Analyze: Common Mode vs. Differential Instrumentation Amps Optoisolators VCOs & PLLs Other Special ICs.
McGraw-Hill © 2008 The McGraw-Hill Companies, Inc. All rights reserved. Principles of Electronic Communication Systems FM Circuits.
A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Improved Effective Phase Resolution Chang-Kyung Seong 1), Seung-Woo Lee.
A Wide-Input-Range 8 bit Cyclic TDC Reportor : Zhu kunkun.
Oct 13, 2005CS477: Analog and Digital Communications1 PLL and Noise in Analog Systems Analog and Digital Communications Autumn
UNIT EIGHT: Waves  Chapter 24 Waves and Sound  Chapter 25 Light and Optics.
SoC Clock Synchronizers Project Elihai Maicas Harel Mechlovitz Characterization Presentation.
Flip Flops 4.1 Latches and Flip-Flops 4 ©Paul Godin Created September 2007 Last edit Sept 2009.
A sequential logic circuit (a.k.a. state machine) consists of both combinational logic circuit(s) and memory devices (flip flops). The combinational circuits.
EE 4BD4 Lecture 14 Position Sensors 1. Types of Sensors Potentiometers and linear resistors Capacitive sensors (mm distances, e.g. capacitive microphone)
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
S Transmission Methods in Telecommunication Systems (4 cr) Carrier Wave Modulation Systems.
End OF Column Circuits – Design Review
Sequential Logic An Overview
EI205 Lecture 8 Dianguang Ma Fall 2008.
DR S. & S.S. GHANDHY ENGINEENRING COLLEGE
Figure 4–1 Communication system.
D Flip-Flop.
Introduction to Sequential Logic Design
Phase-Locked Loop Design
Lecture No. 24 Sequential Logic.
Digital Logic & Design Dr. Waseem Ikram Lecture No. 31.
Unit 7 Sequential Circuits (Flip Flop)
Instructor: Alexander Stoytchev
C.2.10 Sample Questions.
OCT (Optical Coherence Tomography) Time domain Frequency domain Coherence length.
C.2.8 Sample Questions.
C.2.8 Sample Questions.
Forward Design by state transition table, and state graph
A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC
Lecture 22: PLLs and DLLs.
A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC
Presentation transcript:

Oct 2013Sharif University of Technology1 Simple Half-rate phase detector detects but has no reference! Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology2 Half-rate linear phase detector detects plus producing a reference! But do I believe it? Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology3 Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology4 Frequency detector shows that slow and fast clocks can have a bang bang performance using three flip-flops. Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology5 CDR sample architecture 1. Frequency Detector and Phase Detector both used. Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology6 CDR Sample Architecture 2. FD plus PD! Coarse plus fine VCO Control Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology7 CDR Sample Architecture 3. Using two coupled VCOs Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology8 CDR Sample Archtecture 4. Using External reference. Optical Communications: Circuits, Systems and Devices

Oct 2013Sharif University of Technology9 Questions ?