NetPerL Seminar Hardware/Software Co-Design Giovanni DeMichell, Rajesh Gupta Proceedings of the IEEE, No 3, March 1997 Presented By: Jim Harris July 23, 2002 4/24/2019 Cal Poly Network Performance Research Group

Cal Poly Network Performance Research Group Background Peak citations in 1994 and 1997 Now FPGA technology and design tools Paper establishes general framework for current digital system design CAD practices Definition in paper: “Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through concurrent design” 4/24/2019 Cal Poly Network Performance Research Group

Approach to Discussion Present topics in paper Review current technology of Altera NIOS Analog versus digital system design Interface to continuous physical world D/A and A/D now greater than 1 GHz Microwaves and photonics for high frequencies Moore’s Law for at least ten years more 4/24/2019 Cal Poly Network Performance Research Group

Distinquishing Features of Electronic Systems Applications Domains Embedded Self-contained Lumped Degree of Programmabilty Access to programming: application developers, system integrators, component manufacturers Levels of programming: application, instruction, hardware 4/24/2019 Cal Poly Network Performance Research Group

Cal Poly Network Performance Research Group Application Domains 4/24/2019 Cal Poly Network Performance Research Group

Distinquishing Features of Electronic Systems (cont) ISA: instruction set architecture Boundary between hardware and software Reconfigurable circuits: hardware-level programming Nonrecurrent engineering (NRE) cost Implementation features: lumped systems Components to systems on a chip 4/24/2019 Cal Poly Network Performance Research Group

Co-Design Problems and Design Approaches Co-design of embedded systems See figure Co-design of ISA Co-design of reconfigurable systems FPGA technology Note that FPGA technology dominates now Information and DSP processing Embedded control systems Path to ASIC implementation for large volumes 4/24/2019 Cal Poly Network Performance Research Group

Embedded Control System Essential Parts 4/24/2019 Cal Poly Network Performance Research Group

Design of Hardware/Software Systems Involves modeling, validation, and implementation Hardware/Software partitioning Architectural assumptions: co-processing Partitioning objectives: performance Partitioning strategies: heuristics (engineering) 4/24/2019 Cal Poly Network Performance Research Group

Design of Hardware/Software Systems (cont) Scheduling: “assigning an execution start time to each task in a set, where tasks are linked by some relation” Elementary: operations (instructions) Ensemble of elementary operations: processes (program) 4/24/2019 Cal Poly Network Performance Research Group

Design of Hardware/Software Systems (cont) Scheduling Operation scheduling in hardware: minimize the overall execution latency Instruction scheduling in computers Process scheduling in different operating systems 4/24/2019 Cal Poly Network Performance Research Group

Accomplishments/Conclusion Concepts have allowed “time to market” to be significantly reduced: multiple years to months Tracy Kidder; Soul of a New Machine; Atlantic Monthly Press; 1981 Data General minicomputer one-year development with PLD’s 4/24/2019 Cal Poly Network Performance Research Group

Cal Poly Network Performance Research Group Nios Embedded Processor System Development The Nios® embedded processor is a soft processor optimized for Altera® programmable logic and system-on-a-programmable-chip (SOPC) solutions. Nios embedded processor-based systems are created using Altera's SOPC Builder system development tool. Current Technology Altera Excalibur NIOS FPGA environment Microtronix Linux Development Kit NIOS Excalibur Board Added SDRAM, FLASH memory IDE interface uClinux port Development environment with cross-compiler: CYGWIN Xilinx has competing technology 4/24/2019 Cal Poly Network Performance Research Group

System on programmable Chip Nios Embedded Processor System Development The Nios® embedded processor is a soft processor optimized for Altera® programmable logic and system-on-a-programmable-chip (SOPC) solutions. Nios embedded processor-based systems are created using Altera's SOPC Builder system development tool. Nios Embedded Processor System Development The Nios® embedded processor is a soft processor optimized for Altera® programmable logic and system-on-a-programmable-chip (SOPC) solutions. Nios embedded processor-based systems are created using Altera's SOPC Builder system development tool. System on programmable Chip 4/24/2019 Cal Poly Network Performance Research Group

NIOS Development Board 4/24/2019 Cal Poly Network Performance Research Group

Cal Poly Network Performance Research Group NIOS Block Diagram 4/24/2019 Cal Poly Network Performance Research Group