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Dynamically Reconfigurable Architectures: An Overview Juanjo Noguera Dept. Computer Architecture (DAC-UPC)

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Presentation on theme: "Dynamically Reconfigurable Architectures: An Overview Juanjo Noguera Dept. Computer Architecture (DAC-UPC)"— Presentation transcript:

1 Dynamically Reconfigurable Architectures: An Overview Juanjo Noguera Dept. Computer Architecture (DAC-UPC) jnoguera@ac.upc.es

2 2 n Introduction n Reconfigurable Computing Reconfigurable devices and systemsReconfigurable devices and systems Reconfigurable Systems ClassificationReconfigurable Systems Classification Reconfiguration MethodsReconfiguration Methods n Reconfigurable Instruction Set Processors ASIP-based approachASIP-based approach Coprocessor-based approachCoprocessor-based approach n Conclusions Outline

3 3 n Reconfigurable Computing (RC) is an emerging paradigm for digital systems design n Technology improvements have made possible new programmable logic devices (FPGAs, CPLDs) n Objective of the talk: Give an overview of RC concepts and introduce the Reconfigurable Instruction Set Processors. Introduction

4 4 Introduction (II) n RC objectives: Specialization, performance, flexibility n Basic idea: “Programmable Hardware”  Specialization l  Performance l  Power consumption l  Flexibility l  Programming

5 5 Introduction (III) n RC comparison versus other alternatives Application Specific Systems General Purpose Systems Cost Performance Reconfigurable Computing Performance Flexibility, Power GPP ASIC DSP RC

6 6 n Introduction n Reconfigurable Computing Reconfigurable devices and systemsReconfigurable devices and systems Reconfigurable Systems ClassificationReconfigurable Systems Classification Reconfiguration MethodsReconfiguration Methods n Reconfigurable Instruction Set Processors ASIP-based approachASIP-based approach Coprocessor-based approachCoprocessor-based approach n Conclusions Outline

7 7 n General device architecture Reconfigurable Devices Reconfigurable Computing Logic Bloc Interconnection Structure I/O Bloc

8 8 n Routing strategies Reconfigurable Devices (II) Reconfigurable Computing A B C A B C Continuous Routing Structured Routing

9 9 n SRAM based devices with infinite number of reconfigurations Reconfigurable Devices (III) Reconfigurable Computing Configuration Bitstream 110011101... App 1 -> Bitstream 1 App 2 -> Bitstream 2 App n -> Bitstream n Reconfigurable Device

10 10 n Rapid System (ASIC) Prototyping Reconfigurable Systems (I) Reconfigurable Computing PLD CPUPLD

11 11 n Reconfigurable Systems Classification Reconfigurable Systems (II) Reconfigurable Computing I/O PLD RAM PLD CPU RAM PLD RAM (c) (d) (b) (a) Host Computer SYSTEM BUS

12 12 Reconfiguration Methods (I) Reconfigurable Computing n Compile Time Reconfiguration (CTR) Device configuration is fixed during application run time executionDevice configuration is fixed during application run time execution n Run Time Reconfiguration (RTR) Device configuration changes during application run time executionDevice configuration changes during application run time execution n RTR strategies Global RTRGlobal RTR Partial RTRPartial RTR

13 13 n Global Run Time Reconfiguration (Single context) Reconfiguration Methods (II) Reconfigurable Computing #1 #2 #3 #4 Application #1 Reconfiguration Contexts Dynamically Reconfigurable Device Reconfiguration Execution #2 Reconfiguration Execution Reconfiguration #4 Execution

14 14 n Partial Run Time Reconfiguration (Multiple context) Reconfiguration Methods (III) Reconfigurable Computing #1 #2 #3 #4 Aplicació Reconfiguration Contexts Dynamically Reconfigurable Device #4 #1 #3 Reconfiguration #4 #1 #2

15 15 n Run-Time Reconfiguration Challenges Temporal PartitioningTemporal Partitioning Context Scheduling (static)Context Scheduling (static) n Reconfiguration Latency Overhead Configuration Pre-fetchingConfiguration Pre-fetching Configuration CachingConfiguration Caching Configuration CompressionConfiguration Compression Reconfiguration Methods (IV) Reconfigurable Computing

16 16 n Introduction n Reconfigurable Computing Reconfigurable devices and systemsReconfigurable devices and systems Reconfigurable Systems ClassificationReconfigurable Systems Classification Reconfiguration MethodsReconfiguration Methods n Reconfigurable Instruction Set Processors ASIP-based approachASIP-based approach Coprocessor-based approachCoprocessor-based approach n Conclusions Outline

17 17 n By including reconfigurability we can increase flexibility with high specialization Introduction Reconfigurable Instruction Set Processors ProcessorPLD Reconfigurable Processor

18 18 n Coprocessor based approach n ASIP based approach Introduction (II) Reconfigurable Instruction Set Processors · · · Task 1 Task K · · · Task K+1Task N SoftwareHardware Task 1Task 2Task N Software Hardware · · ·

19 19 n Typical example: CPU + PCI board Altera ARC-PCIAltera ARC-PCI Compaq PametteCompaq Pamette n System on Chip (SoC) Altera´s Excalibur deviceAltera´s Excalibur device Chameleon Systems, Inc.Chameleon Systems, Inc. Coprocessor based approach (I) Reconfigurable Instruction Set Processors

20 20 n Altera ARC-PCI Coprocessor based approach (II) Reconfigurable Instruction Set Processors

21 21 n Compaq Pamette Coprocessor based approach (III) Reconfigurable Instruction Set Processors

22 22 n Altera´s Excalibur device Embedded Processor: ARM, MIPS or NIOSEmbedded Processor: ARM, MIPS or NIOS Coprocessor based approach (IV) Reconfigurable Instruction Set Processors

23 23 n Chameleon Systems, Inc. Coprocessor based approach (V) Reconfigurable Instruction Set Processors

24 24 n Reconfigurable unit within CPU ASIP based approach (I) Reconfigurable Instruction Set Processors Fetch Decode Issue Integer Unit FP Unit Branch Unit LD/ST Unit Reconfigurable Unit

25 25 n Challenge: CAD tools ASIP based approach (II) Reconfigurable Instruction Set Processors C Code Compiler Assembly Code Instruction Description (Configuration bits)

26 26 ASIP based approach (III) Reconfigurable Instruction Set Processors C Parsing Optimizations Inst. Identification Inst. Selection Config. Scheduling Code Generation C Code Assembly Code Hardware Generation Configuration bits Hardware Estimator Compiler Structure

27 27 n Example: Philips CinCISe Architecture ASIP based approach (II) Reconfigurable Instruction Set Processors Encoded Instruction Word Register File ALU RFU MUX 5 5 5 4 32

28 28 n Application example: DES & A5 encryptation algorithms ASIP based approach (III) Reconfigurable Instruction Set Processors 27 26 25 23 22 30 7 6 5 4 3 2 27 26 25 22 XOR srl $13, $2, 20 andi $25, $13, 1 srl $14, $2, 21 andi $24, $14, 6 or $15, $25, $24 srl $13, $2, 22 andi $14, $13, 56 or $25, $15, $14 sll $24, $25, 2 srl $24, $5, 18 srl $25, $5, 17 xor $8, $24, $25 srl $9, $5, 16 xor $10, $8, $9 srl $11, $5, 13 xor $12, $10, $11 andi $13, $12, 1

29 29 n Reconfigurable Computing is an emerging and interesting computing paradigm n RC devices and architectures are becoming a reality n There is a big challenge is High-level synthesis (CAD) tools Conclusions

30 30 n What is the future ?? Conclusions (II) Flexibility, Power Performance GPP ASIC DSP RC ?? RC

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