Copyright © 2004 by Miguel A. Marin Revised CMOS CIRCUIT TECHNOLOGY NMOS & PMOS TRANSISTOR SWITCH NMOS & PMOS AS LOGIC CIRCUITS NMOS & PMOS LOGIC GATES CMOS LOGIC GATES POSITIVE & NEGATIVE LOGIC PHYSICAL CHARACTERISTICS PASS-TRANSISTORS PASSING 1S AND 0S TRANSMISSION GATES

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS TRANSISTOR SWITCH NMOS TRANSISTOR SWITCH PMOS TRANSISTOR SWITCH

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS AS LOGIC CIRCUITS NMOS AS LOGIC CIRCUITS: V DD IS THE HIGH VOLTAGE FROM THE POWER SUPPLY 0 VOLTS IS THE LOW VOLTAGE,GROUND POLARITY IN NMOS, WHEN TURNED ON, V D IS PULLED DOWN TO GROUND

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS AS LOGIC CIRCUITS PMOS AS LOGIC CIRCUITS: V DD IS THE HIGH VOLTAGE FROM THE POWER SUPPLY 0 VOLTS IS THE LOW VOLTAGE,GROUND POLARITY IN PMOS, WHEN TURNED ON, V D IS PULLED UP TO V DD

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES NMOS LOGIC GATES: THE NOT GATE THERE IS POWER DISSIPATION IN STEADY STATE V X V f HLHL LHLH

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES NMOS LOGIC GATES: THE NAND GATE THERE IS POWER DISSIPATION IN STEADY STATE IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NAND GATE V X V Y V f L L H H L H HHHLHHHL

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES NMOS LOGIC GATES: THE NOR GATE THERE IS POWER DISSIPATION IN STEADY STATE IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NOR GATE V X V Y V f L L H H L H HLLLHLLL

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES NMOS LOGIC GATES: THE AND GATE THERE IS POWER DISSIPATION IN STEADY STATE IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE AND GATE V X V Y V f L L H H L H LLLHLLLH

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES NMOS LOGIC GATES: SUMMARY THERE IS POWER DISSIPATION IN STEADY STATE

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES PMOS LOGIC GATES: THE NOT GATE THERE IS POWER DISSIPATION IN STEADY STATE V X V f HLHL LHLH

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES PMOS LOGIC GATES: THE NAND GATE THERE IS POWER DISSIPATION IN STEADY STATE IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NAND GATE V X V Y V f L L H H L H HHHLHHHL

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES PMOS LOGIC GATES: THE NOR GATE THERE IS POWER DISSIPATION IN STEADY STATE IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NOR GATE V X V Y V f L L H H L H HLLLHLLL

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES PMOS LOGIC GATES: THE AND GATE THERE IS POWER DISSIPATION IN STEADY STATE IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE AND GATE V X V Y V f L L H H L H LLLHLLLH

Copyright © 2004 by Miguel A. Marin Revised NMOS & PMOS LOGIC GATES PMOS LOGIC GATES: SUMMARY THERE IS POWER DISSIPATION IN STEADY STATE

Copyright © 2004 by Miguel A. Marin Revised CMOS LOGIC GATES TO EVOID STEADY STATE POWER DISSIPATION THE PULL-UP DEVICE, USED IN NMOS LOGIC GATES, IS REPLACED BY A PULL-UP NETWORK BUILT WITH PMOS TRANSISTORS. THE PULL-DOWN DEVICE, USED IN PMOS LOGIC GATES, IS REPLACED BY A PULL-DOWN NETWORK BUILT WITH NMOS TRANSISTORS.

Copyright © 2004 by Miguel A. Marin Revised CMOS LOGIC GATES CMOS CIRCUIT : NOT GATE VXVX T 1 T 2 V f LON OFFH HOFF ONL

Copyright © 2004 by Miguel A. Marin Revised CMOS LOGIC GATES CMOS CUIRCUIT V X V Y T 1 T 2 T 3 T 4 V f L L H H L H ON ON OFF OFF ON OFF OFF ON OFF ON ON OFF OFF OFF ON ON HHHLHHHL

Copyright © 2004 by Miguel A. Marin Revised CMOS LOGIC GATES PROCEDURE TO CONSTRUCT CMOS COMPLEX LOGIC GATES F. THE PULL-UP NETWORK IS CONSTRUCTED WITH F USING ONLY PMOS TRANSISTORS. THE POLARITIES OF THE VARIABLES ARE COMPLEMENTED THE PULL-DOWN NETWORK IS CONSTRUCTED WITH !F USING ONLY NMOS TRANSISTORS. PUN AND PDN ARE MUTUALLY EXCLUSIVE. THEY CANNOT BE CONDUCTING AT THE SAME TIME. THE OUTPUT V f CANNOT BE HIGH AND LOW SIMULTANEOUSLY. IF BOTH NETWORKS ARE NOT CONDUCTING, THEN THE OUTPUT IS SAID TO BE FLOWTING OR PESENTING HIGH IMPIDANCE. THE POLARITY OF THE INPUT VARIABLES IS THE SAME FOR BOTH NETWORKS.

Copyright © 2004 by Miguel A. Marin Revised CMOS LOGIC GATES GENERAL STRUCTURE OF A CMOS COMPLEX LOGIC GATE CIRCUIT F.

Copyright © 2004 by Miguel A. Marin Revised CMOS LOGIC GATES EXAMPLE OF A CMOS COMPLEX LOGIC GATE CIRCUIT F. DESIGN A CMOS CIRCUIT PRODUCING THE FUNCTION F(A,B,C,D) = !A + (!B +!C) !D. !F(A,B,C,D) = A(BC + D) PULL-UP NETWORK PULL-DOWN NETWORK

Copyright © 2004 by Miguel A. Marin Revised POSITIVE & NEGATIVE LOGIC THE BEHAVIOR OF A SWITCHING DEVICE, LIKE A CMOS GATE, IS GIVEN IN TERMS OF HIGH AND LOW VOLTAGES. FOR A GIVEN DEVICE, THIS BEHAVIOR IS UNIQUE. HOWEVER, ITS LOGIC BEHAVIOR CAN BE DEFINED EITHER WITH POSITIVE LOGIC CONVENCTION: HIGH FOR 1 ; LOW FOR 0 OR WITH NEGATIVE LOGIC CONVENCTION: HIGH FOR 0; LOW FOR 1. IN GENERAL THE LOGIC BEHAVIOR OF A SWITCHING DEVICE MAY BE DIFFERENT IN POSITIVE AND NEGATIVE LOGICS. FOR EXAMPLE, THE CMOS DEVICE ON NEXT SLIDE REPRESENTS THE NAND GATE IN POSITIVE LOGIC AND THE NOR GATE IN NEGATIVE LOGIC

Copyright © 2004 by Miguel A. Marin Revised POSITIVE & NEGATIVE LOGIC EXAMPLE OF POSITIVE AND NEGATIVE LOGICS

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS TRANSISTOR AS A SWITCH STATIC CURRENT NOISE MARGIN DYNAMIC OPERATION PROPAGATION DELAY POWER DISSIPATION FAN-IN/FAN-OUT

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS TRANSISTOR AS A SWITCH: STATIC CURRENT; THE NOT GATE WHEN THE TRASISTOR IS CUT-OFF, IT CAN CONDUCT A VERY LOW CURRENT, CALLED LEAKAGE CURRENT

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS VOLTAGE TRANSFER CHARACTERISTIC V T is the threshold voltage ~ 0.2 V DD V OH is the output high voltage = V DD V OL is the output low voltage = 0.2 volts The plot of V f versus V x shows the voltage transfer characteristic

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS NOISE MARGIN TWO MARGINS: NM L, NM H BY DEFINITION: NM L = V IL - V OL ; NM H = V OH – V IL EXAMPLE: FOR CMOS SWITCHING CIRCUITS LET V OH = V DD AND V OL = 0 v. Finding the two points where SLOPE = -1 V IL ~ 1/8 (3 V DD + 2 V T ), V IH ~ 1/8 (5 V DD - 2 V T ) IF V T = 0.2 V DD THEN NM L = NM H = V DD For V DD = 5 v. NM L = NM H = 2.1 v. For V DD = 3.3 v. NM L = NM H = 1.4 v.

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS DYNAMIC OPERATION LET US CONSIDER TWO INVERTERS CONNECTED IN CASCADE CAPACITIVE LOAD AT NODE A IS DUE TO SILICON CONSTRUCTION OF TRANSISTOR. IT IS CALLED PARASITIC OR STRAY CAPACITANCE

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS DYNAMIC OPERATION (Continues) Each transistor contributes a GATE CAPACITANCE C g = W. L. C ox where C ox is called OXIDE CAPACITANCE and depends on technology and is given in f F/µm 2 units Other capacitance is due to wiring. ALL THESE CAPACITANCE ARE REPRESENTED BY C. C AFFECTS THE SPEED OF OPERATION OF THE CIRCUIT

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS PROPAGATION DELAY is defined as the time required to discharge C through the NMOS transistor voltage V DD /2 and it is given by the formula or where k n is the process transconductance parameter, W the width and L the length of the substrate. For PMOS, the propagation delay is computed by choosing the corresponding k n.

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS POWER DISSIPATION Is the amount of power used by a transistor. It must be small Consider the inverter: For V x = 0, no current flows, and therefore, no power is consumed. For V x = 5 v., the current flowing is I SAT, the power dissipated is P S = I SAT V DD. If I SAT = 0.2 mA, then P S = 0.2 x 5 = 1.0 mW inverters will dissipate 10 watts

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS POWER DISSIPATION (Continues) Steady state power dissipation: is the power dissipated in steady state current flow. Dynamic power dissipation: is the power dissipated due to the switching action. NMOS circuits present STATIC and DYNAMIC power dissipation PMOS circuits present STATIC and DYNAMIC power dissipation CMOS circuits present ONLY DYNAMIC power dissipation

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS POWER DISSIPATION (Continues) CMOS CIRCUITS POWER DISSIPATION: THE ENERGY STORED IN THE CAPACITOR IS E =(C V DD 2 )/2 FOR CHARGING AND DISCHARGING THE CAPACITOR, THE TOTAL ENERGY IS 2 E = C V DD 2. POWER = ENERGY PER UNIT TIME IF THE CYCLE TIME (CHARGE – DISCHARGE PER SECOND) IS EQUAL TO f, THEN THE DYNAMIC POWER CONSUMED IS P D = f C V DD 2

Copyright © 2004 by Miguel A. Marin Revised PHYSICAL CHARACTERISTICS FAN-IN/FAN-OUT FAN-IN of a circuit is the number of its inputs. It is given by the formula: where k is the number of inputs and C is the equivalent capacitance at the output of the gate FAN-OUT of a circuit is the maximum number of circuits, n, that can be connected to its output. Then, the capacitor in the above equation is C n = n x C. The propagation delay is computed by the same formula. NANDS with small FAN-IN are constructed with NMOS transistors NORS with large FAN-IN are constructed with NMOS transistors: k transistors in parallel ~ k x W; C, however, increases the load.

Copyright © 2004 by Miguel A. Marin Revised PASS-TRANSISTORS PASSING 1S AND 0 Let us consider the following two configurations V A = V DD – V T V B is not quite equal to 0 v NOT FULLY PASSING V DD NOT FULLY PASSING 0 v. THIS IS DUE TO WHAT IS CALLED BODY EFFECT. BOTH SUBSTRATES ARE BIASED TO V DD WHICH INCREASES THE THRESHOLD VOLTAGE, V T, BY A FACTOR OF 1.5 V..

Copyright © 2004 by Miguel A. Marin Revised TRANSMISSION GATES A TRANSMISSION GATE (T-GATE) IS A CMOS CIRCUIT THAT PASSES, EQUALLY WELL, THE HIGH AND THE LOW VOLTAGES. BOTH PATHS ARE EITHER SIMULTANEOUSLY CONNECTING OR SIMULTANEOUSLY DISCONECTING X TO F. A T-GATE DRIVES ITS OUTPUT EITHER TO LOW OR TO HIGH EQUALLY WELL. EXAMPLE: SF 0101 HIGH IMPEDANCE: Z X

Copyright © 2004 by Miguel A. Marin Revised TRANSMISSION GATES ANOTHER EXAMPLE: EX-OR GATE F = A B THE SHANNON EXPANSION GIVES F = A [!B] + !A [B]