CMOS Layers n-well process p-well process Twin-tub process ravikishore

MOSFET Layers in an n-well process p-substrate n+ p+ n-well Gate NMOS PMOS FOX MOSFET Layers in an n-well process ravikishore

Layer Types p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide Insulated glass Provide electrical isolation ravikishore

Top view of the FET pattern PMOS NMOS NMOS PMOS n+ n+ p+ p+ n-well ravikishore

Metal Interconnect Layers Metal layers are electrically isolated from each other Electrical contact between adjacent conducting layers requires contact cuts and vias ravikishore

Metal Interconnect Layers Ox3 Via Metal2 Active contact Ox2 Metal1 Ox1 n+ p-substrate n+ n+ n+ ravikishore

CMOS Gate Design A 4-input CMOS NOR gate

Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network a.k.a. static CMOS X (crowbar) Pull-down ON 1 Z (float) Pull-down OFF Pull-up ON Pull-up OFF

Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON

Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel

Compound Gates Compound gates can do any inverting function Ex: AND-AND-OR-INV (AOI22)

Example: O3AI

Example: O3AI

Pass Transistors Transistors can be used as switches

Pass Transistors Transistors can be used as switches

Signal Strength Strength of signal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus NMOS are best for pull-down network Thus PMOS are best for pull-up network

Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

Tristates Tristate buffer produces Z when not enabled 1 Z Y A EN

Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y (after several stages, the noise may degrade the signal beyond recognition)

Tristate Inverter Tristate inverter produces restored output Note however that the Tristate buffer ignores the conduction complement rule because we want a Z output

Tristate Inverter Tristate inverter produces restored output Note however that the Tristate buffer ignores the conduction complement rule because we want a Z output

Multiplexers 2:1 multiplexer chooses between two inputs X 1 Y D0 D1 S

Multiplexers 2:1 multiplexer chooses between two inputs 1 X Y D0 D1 S

Gate-Level Mux Design How many transistors are needed?

Gate-Level Mux Design How many transistors are needed? 20

Transmission Gate Mux Nonrestoring mux uses two transmission gates

Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors

Inverting Mux Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter

4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects

4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates

D Latch When CLK = 1, latch is transparent Q follows D (a buffer with a Delay) When CLK = 0, the latch is opaque Q holds its last value independent of D a.k.a. transparent latch or level-sensitive latch

D Latch Design Multiplexer chooses D or old Q Old Q

D Latch Operation

D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

D Flip-flop Design Built from master and slave D latches A “negative level-sensitive” latch A “positive level-sensitive” latch

Holds the last value of NOT(D) D Flip-flop Operation Inverted version of D Holds the last value of NOT(D) Q -> NOT(NOT(QM))

Race Condition Back-to-back flops can malfunction from clock skew Second flip-flop fires Early Sees first flip-flop change and captures its result Called hold-time failure or race condition

Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew Good for safe design Industry manages skew more carefully instead

Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Must follow a technology rule Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

Example: Inverter

Layout using Electric Inverter, contd..

Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32  by 40 

NAND3 (using Electric), contd.

Interconnect Layout Example Gate contact Metal1 Metal2 Metal1 MOS Active contact ravikishore

Designing MOS Arrays A B C y x A B C y x ravikishore

Parallel Connected MOS Patterning x x A B A B X X X y y ravikishore

Alternate Layout Strategy x x X X A B A B X X y y ravikishore

Basic Gate Design Both the power supply and ground are routed using the Metal layer n+ and p+ regions are denoted using the same fill pattern. The only difference is the n-well Contacts are needed from Metal to n+ or p+ ravikishore

The CMOS NOT Gate Contact Cut Vp Vp X n-well X X X Gnd Gnd ravikishore

Alternate Layout of NOT Gate Vp Vp X X X X Gnd Gnd ravikishore

NAND2 Layout Vp Gnd Vp X X X X X Gnd ravikishore

NOR2 Layout Vp Gnd Vp X X X X X Gnd ravikishore

NAND2-NOR2 Comparison X Vp Gnd X Vp Gnd MOS Layout Wiring ravikishore

General Layout Geometry Vp Shared drain/ source Individual Transistors Shared Gates Gnd ravikishore

Graph Theory: Euler Path Vp x Vertex b c x a Edge Out y c y Vertex a b Gnd ravikishore

Stick Diagram ravikishore

Stick Diagrams Cartoon of a layout. Shows all components. Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc. ravikishore

Stick Diagrams Metal poly ndiff pdiff Can also draw in shades of gray/line style. ravikishore

Stick Diagrams Buried Contact Contact Cut ravikishore

Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers Vin Vout VDD GND

Wiring Tracks A wiring track is the space required for a wire 4  width, 4  spacing from neighbor = 8  pitch Transistors also consume one wiring track

Well spacing Wells must surround transistors by 6  Implies 12  between opposite transistor flavors Leaves room for one wire track

Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in 

5 V Dep Vout Enh 0V 0 V Vin 5 v 5 v Vin ravikishore

Stick Diagram - Example I NOR Gate OUT B A ravikishore

Stick Diagram - Example II Power A Out C B Ground ravikishore

Points to Ponder be creative with layouts sketch designs first minimize junctions but avoid long poly runs have a floor plan plan for input, output, power and ground locations ravikishore

The End ravikishore