1. CSCE 612: VLSI System Design Instructor: Jason D. Bakos

2. VLSI System Design 2 Elements

3. VLSI System Design 3 Semiconductors Silicon is a group IV element (4 valence electrons, shells: 2, 8, 18, …) –Forms covalent bonds with four neighbor atoms (cubic crystal lattice) –Si is a poor conductor, but conduction characteristics may be altered –Add impurities/dopants (replaces silicon atom in lattice): Makes a better conductor Group V element (phosphorus/arsenic) => 5 valence electrons –Leaves an electron free => n-type semiconductor (electrons, negative carriers) Group III element (boron) => 3 valence electrons –Borrows an electron from neighbor => p-type semiconductor (holes, positive carriers) forward bias reverse bias + + + - - - ------ ++++++ P-N junction drift +--+

4. VLSI System Design 4 MOSFETs Diodes not very useful for building logic Metal-oxide-semiconductor structures built onto substrate –Diffusion: Inject dopants into substrate –Oxidation: Form layer of SiO 2 (glass) –Deposition and etching: Add aluminum/copper wires body/bulk GROUND PFET/NFETPMOS/PFET channel shorter length, faster transistor (dist. for electrons) body/bulk HIGH positive charge (Vdd) negative charge (rel. to body) (GND) (S/D to body is reverse-biased) - - - + + + - - - current

5. VLSI System Design 5 FETs as Switches NFETs and PFETs can act as switches pull-up OFF pull-up ON pull-down OFF Z (floating) 1 pull-down ON 0smokin’! bulk node not shown CMOS logic CMOS: assuming PU and PN network are perfect switches and switch simultanously, no current flow and no power consumption! “and structure”“or structure”

6. VLSI System Design 6 Logic Gates inv NAND2 NAND3 NOR2 DeMorgan’s Law NMOS devices (positive logic) form pull- down network PMOS devices (negative logic) form pull- up network Implication: CMOS transistor-level logic gates implement functions where may the inputs are inverted (inverting gates) Add inverter at inputs/outputs to create non-inverting gate

7. VLSI System Design 7 Compound Gates Combine parallel and series structures to form compound gates –Example: –Use DeMorgan’s law to determine complement (pull- down network): Y A A B B C C D D

8. VLSI System Design 8 Pass Transistors/Transmission Gates NMOS passes strong 0 (pull-down) PMOS passes strong 1 (pull-up) Pass transistor:Transmission gate:

9. VLSI System Design 9 Tristates

10. VLSI System Design 10 Multiplexer Transmission gate multiplexer Inverting multiplexer

11. VLSI System Design 11 Multiplexer 4-input multiplexer

12. VLSI System Design 12 Latches Positive level-sensitive latch

13. VLSI System Design 13 Latches Positive edge-sensitive latch

14. VLSI System Design 14 IC Fabrication Inverter cross-section field oxide

15. VLSI System Design 15 IC Fabrication Inverter cross-section with well and substrate contacts (ohmic contact)

16. VLSI System Design 16 IC Fabrication Chips are fabricated using set of masks –Photolithography Inverter uses 6 layers: –n-well, poly, n+ diffusion, p+ diffusion, contact, metal

17. VLSI System Design 17 IC Fabrication Furnace used to oxidize (900-1200 C) Mask exposes photoresist to light, allowing removal HF acid etch piranha acid etch diffusion (gas) or ion implantation (electric field) HF acid etch

18. VLSI System Design 18 IC Fabrication Heavy doped poly is grown with gas in furnace (chemical vapor deposition) Masked used to pattern poly

19. VLSI System Design 19 IC Fabrication Metal is sputtered (with vapor) and pla s ma etched from mask

20. VLSI System Design 20 Layout Design Rules Design rules define ranges for features –Examples: min. wire widths to avoid breaks min. spacings to avoid shorts minimum overlaps to ensure complete overlaps –Measured in microns –Required for resolution/tolerances of masks Fabrication processes defined by minimum channel width –Also minimum width of poly traces –Defines “how fast” a fabrication process is Lambda-based (scalable CMOS) design rules define scalable rules based on (which is half of the minimum channel length) –classes of MOSIS SCMOS rules: SUBMICRON, DEEP SUBMICRON

21. VLSI System Design 21 Layout Design Rules

22. VLSI System Design 22 Layout Design Rules Transistor dimensions are in W/L ratio –NFETs are usually twice the width –PFETs are usually twice the width of NFETs Holes move more slowly than electrons (must be wider to deliver same current)

23. VLSI System Design 23 Layout 3-input NAND

24. VLSI System Design 24 Design Flow Design flow is a sequence of steps for design and verification In this course: –Describe behaviors with VHDL/Verilog code –Simulate behavioral designs –Synthesize behaviors into cell-level netlists –Simulate netlists with cell-delay models –Place-and-route netlists into a physical design –Simulate netlists with cell-delay models and wire-delay models Need to define a cell library: –Function –Electrical characteristics of each cell –Layout

25. VLSI System Design 25 Cell Library (Snap Together) Layout