FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison, Part 2

Fundamentals of FPGA Design 1 day Designing for Performance 2 day s Advanced FPGA Implementation 2 days Intro to VHDL or Intro to Verilog 3 days FPGA and ASIC Technology Comparison FPGA vs. ASIC Design Flow ASIC to FPGA Coding Conversion Virtex-5 Coding Techniques Spartan-3 Coding Techniques CurriculumPath for ASIC Design FPGA and ASIC Technology Comparison

If you are an experienced ASIC designer transitioning to FPGAs, this course will help you reduce your learning curve by leveraging your ASIC experience Careful attention to how FPGAs are different than ASICs will help you create a fast and reliable FPGA design Welcome

Describe how a simple logic implementation can differ between ASIC and FPGAs Recognize gate counts as an estimation of design size Explain some of the FPGA design practices you must follow to get peak performance in your FPGA After completing this module, you will able to:

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Gate Comparison In retargeting HDL code for an ASIC design to an FPGA, gate conversion is rarely one to one A 0.13-µ standard cell can have up to 100K gates per mm 2 A Virtex®-5 FPGA has about 20K usable gates per mm 2 Why the difference? Xilinx has programmable logic in addition to the functional logic Routing Multiplexers Configuration memory registers This means built-in design flexibility!

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Gate Translation Separate out logic, flip-flops, RAM, cores, and I/O Partition cores into logic and RAM Assume 6 to 24 gates per LUT (depending on the number of inputs used) RAM bits are equivalent Up to 100 ASIC gates per I/O; translate to IOBs 7 gates per register So what design strategy do you think you need to use? To get the most out of the FPGA try to use as many features as possible, especially the FPGAs dedicated hardware

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved Example ASIC 250K logic gates Four 32-kb blocks of RAM 243 pads, including power and ground FPGA 20,800 to 41,600 LUTs Equivalent Equivalent number of pins Depending on the number of LUTs needed, this design could use a Virtex-5 LX30, LX50, or LX85 FPGA

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved Any ASIC-to-FPGA gate counting method is only a rough estimate. Taking ASIC code directly to an FPGA will not utilize the dedicated resources of the FPGA. Gate Counts Gate counts are influenced by Coding style Metal layers Process geometry Library quality Placement and routing algorithms Core contents (RAM versus gates) I/O requirements Special features CONCLUSION

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved 8-input AND gate AND Gate Example For vec(7.0) assign and_out = & vec; Verilog For vec(7 downto 0) and_out <= vec(0) AND vec(1) AND vec(2) AND vec(3) AND vec(4) AND vec(5) AND vec(6) AND vec(7); VHDL

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved ASIC Implementation 8-input AND gate Two four-input NAND gates feeding a two-input NOR gate Approximate delay in a standard-cell ASIC with 0.13-µ process = 0.47 ns Approximate gate count = 14 Beware of ASIC libraries with very wide gate types!

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved Xilinx Implementation Approximate max delay in a Virtex-5 FPGA = ns Approximate gate count = 18 gates 8-input AND gate implemented in three 4-input LUTs and two logic levels Approximate max delay in a Spartan®-3 FPGA = ns Approximate gate count = 18 gates

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved Question How many 4-input LUTs would be required to implement a 32-input OR gate? How many Logic Levels would they generate?

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved Answer How many 4-input LUTs would be required to implement a 32-input OR gate? 11 How many Logic Levels would they generate? 3 If net delays ~.3 ns and LUT delays ~.2 ns then total delay would be 2(.3) + 3(.2) ~ 1.2 ns …in a Spartan®-3 FPGA How do you think this would be implemented in Virtex-5 with a 6-input LUT? (Answer: 7 LUTs and 2 Logic Levels) LUT

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved Tri-State Busses Some ASIC designs have large tri-state busses There are no tri-state buffers associated with each slice in the newest FPGAs These will have to be re-synthesized and be mapped to LUTs and the F7 and F8 dedicated muxes You may need to code these with a CASE statement and a high-Z output The F7 can implement an 8-to-1 mux The F8 can implement a 16-to-1 mux

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Registered AND gate process (clk) begin if rising_edge(clk) then vec_q <= vec; and_out <= vec_q(0) AND vec_q(1) AND vec_q(2) AND vec_q(3) AND vec_q(4) AND vec_q(5) AND vec_q(6) AND vec_q(7); end if; end process; VHDL (posedge clk) begin vec_q <= vec; and_out <= & vec_q; end Verilog

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved Performance Comparison A comparison of the achieved performance for the registered 8-input AND gate Virtex-5 FPGA ~550 MHz ~88 gates 0.13-µ standard cell ASIC ~850 MHz ~77 gates Typical high-performance frequencies ( no optimization for the FPGA ) Virtex-5 FPGA ~275 MHz for four-levels of LUT (combinatorial) logic 0.13-µ standard cell ASIC ~550 MHz for equivalent logic Dont forget to optimize your HDL code!

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved ASIC versus FPGA Combinatorial logic implemented in an ASIC is typically faster than in an FPGA implementation The fine-grain architecture of an ASIC allows wider input functions to be implemented with significantly less delay ASICs have a dedicated routing structure rather than a programmable routing structure Dont forget to include Xilinx-dedicated resources in your design! Critical paths typically include I/O, RAM, PCI technology, EMAC, and DSP resources Xilinx has dedicated FPGA resources to implement these functions, making these paths equivalent to an ASIC implementation Remember: Xilinx Virtex-5 devices are cutting-edge ASICs

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved Pipelining f MAX = n MHz DQ Two Logic Levels DQ f MAX 2n MHz One Level DQDQDQ

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2009 Xilinx, Inc. All Rights Reserved Sequential Design How do you get high performance from an FPGA? Pipelining For large combinatorial paths, additional registers may need to be inferred to break up combinatorial paths to increase performance This technique increases the size of the design This is not as likely to be needed for Virtex-5 FPGA designs because the Virtex-5 FPGA has a 6-input LUT Evaluate the number of logic levels your design has by generating a timing report from the ISE® Design Suite or your synthesis tool Usually the registers are added at a hierarchical boundary Dont forget to evaluate the number of logic levels for your timing-critical paths!

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2009 Xilinx, Inc. All Rights Reserved Timing Constraints How do you get high performance from an FPGA? Timing constraints Timing constraints communicate the performance goals to the implementation tools Global timing constraints constrain virtually all the paths in your design based on your system frequency, input, and output times (PERIOD, OFFSET IN, OFFSET OUT) Path-specific timing constraints need to be added to constrain multi-cycle paths and false paths Adding timing constraints is essential if you want good system speed!

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Coding Style How do you get high performance out of an FPGA? Coding style has a large impact on the performance Because FPGA combinatorial and routing resources are inherently slower, the HDL coding style needs to be improved Write your code to limit the number of logic levels inferred Learn about proper HDL coding styles by listening to the REL modules Dont waste time! Evaluate your HDL!

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved Synchronous Design How do you get reliability out of an FPGA? Always build a synchronous design Asynchronous circuits are less reliable Lot variations exist for all FPGAs, which means that your design has to be able to work for faster devices Timing constraints Cannot fix asynchronous design problemsonly you can

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2009 Xilinx, Inc. All Rights Reserved Synchronous Design Methodology One clock (or at least as few as possible) Use one edge (all flip-flops use rising or falling edge) Use D-type flip-flops Register the outputs of each behavioral block In place of multiple clocks, use clock enables Synchronize asynchronous signals to the single clock (synchronization circuits) Do NOT create Gated, derived, or divided clocks Local asynchronous set/reset Avoid global asynchronous set/reset Get it right the first time!

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2009 Xilinx, Inc. All Rights Reserved Summary Dont worry too much about gate counting methodologies. They are only rough estimates, anyway Optimize your HDL coding style Instantiate Xilinx-dedicated hardware resources into your design to improve your system speed and maximize what you get from your FPGA Pipeline your timing-critical paths Timing constraints are a primary means for improving system speed Get your design to work properly the first time by designing synchronously

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Xilinx Answers Browser Answers Browser window Enter keywords like pipelining or period constraint Xilinx Training Xilinx tools and architecture courses – Fundamentals of FPGA Design » Learn about synchronous design, global timing constraints, the Architecture Wizard, and the CORE Generator tool – Designing for Performance » Learn about avoiding metastability, path-specific timing constraints, and the Timing Analyzer Free training videos » Learn about proper HDL coding techniques

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2009 Xilinx, Inc. All Rights Reserved Xilinx is disclosing this Document and Intellectual Propery (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (High-Risk Applications). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. Trademark Information