Today’s Lab Start working with Xilinx

Slides:

Advertisements

Similar presentations

HDL Programming Fundamentals

Advertisements

Xilinx 6.3 Tutorial Integrated Software Environment (ISE) Set up basic environment Select Gates or Modules to Be simulated (Insert Program Code) Run Waveform.

Verilog Section 3.10 Section 4.5. Keywords Keywords are predefined lowercase identifiers that define the language constructs – Key example of keywords:

ADDER, HALF ADDER & FULL ADDER

Verilog in transistor level using Microwind

CDA 3100 Recitation Week 11.

//HDL Example 4-10 // //Gate-level description of circuit of Fig. 4-2 module analysis (A,B,C,F1,F2); input.

The Verilog Hardware Description Language

Supplement on Verilog adder examples

Verilog Descriptions of Digital Systems

Combinational Logic with Verilog Materials taken from: Digital Design and Computer Architecture by David and Sarah Harris & The Essentials of Computer.

Figure 4.1. The function f (x1, x2, x3) =  m(0, 2, 4, 5, 6).

Full Adder Section 4.5 Spring, 2014 J.Ou. Schedule 62/3MondayBinary addition: full adder 72/5WednesdayBinary addition: full adder/four-bit adder L2/6ThursdayLab.

1 Brief Introduction to Verilog Weiping Shi. 2 What is Verilog? It is a hardware description language Originally designed to model and verify a design.

4 bit Full Adder Layout and Analysis using Lasi and WinSpice

Binary Addition. Binary Addition (1) Binary Addition (2)

Half Adder ( / ) Structural description: Data flow description:

ECE – 329 Fall 2007 Lab Manual for Xilinx Example: Design and simulation of a Half Adder Instructor: Dr.Botros.

ENEE 408C Lab Capstone Project: Digital System Design Verilog Tutorial Class Web Site:

ENEE 408C Lab Capstone Project: Digital System Design Spring 2005 Class Web Site: e408c.

ENEE 408C Lab Capstone Project: Digital System Design Spring 2006 Class Web Site:

Calculator Lab Overview Note: Slides Updated 10/8/12

 Delay values control the time between the change in a right-hand-side operand and when the new value is assigned to the left- hand side.  Three ways.

Verilog Intro: Part 2. Procedural Blocks There are two types of procedural blocks in Verilog. – initial for single-pass behavior: initial blocks execute.

Binary Addition CSC 103 September 17, 2007.

XOR and XNOR Logic Gates. XOR Function Output Y is TRUE if input A OR input B are TRUE Exclusively, else it is FALSE. Logic Symbol  Description  Truth.

ADDERS Half Adders Recall that the basic rules of binary addition are as indicated below in Table 2-9. A circuit known as the half-adder carries out these.

VHDL TUTORIAL Preetha Thulasiraman ECE 223 Winter 2007.

Figure 5.1. Conversion from decimal to binary.. Table 5.1. Numbers in different systems.

Figure 5.1. Conversion from decimal to binary.. Table 5.1. Numbers in different systems.

1 Adders & Subtractors Adders –An adder is a combinational logic circuit that performs the addition of 2 binary numbers (A & B) to generate the sum (S)

CPEN Digital System Design

Module 2.1 Gate-Level/Structural Modeling UNIT 2: Modeling in Verilog.

Use CMOS Transistors to bit a 4-bit Adder. NAND2 symbol Schematic.

Module 1.2 Introduction to Verilog

Number Systems and Circuits for Addition Lecture 5 Section 1.5 Thu, Jan 26, 2006.

LECTURE VII SECTION 4.12 PART 1 MODELS OF COMBINATIONAL CIRCUITS.

ECE 2372 Modern Digital System Design Section 4.8 Xilinx Schematic Capture Simulation Tutorial.

Chapter 2: Structural Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-1 Chapter 2a: Structural Modeling.

1 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here.

Number Systems and Circuits for Addition – Binary Adders Lecture 6 Section 1.5 Fri, Jan 26, 2007.

Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Introduction to Verilog. Data Types A wire specifies a combinational signal. – Think of it as an actual wire. A reg (register) holds a value. – A reg.

Introduction to Verilog Section Outline Set Up the Environment Your First Verilog File Set Up the Test Bench Running the Simulation.

How does a Computer Add ? Logic Gates within chips: AND Gate A B Output OR Gate A B Output A B A B

Chapter1: Introduction Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 1-1 Chapter 1: Introduction Prof. Ming-Bo.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.

Introduction to Verilog. Structure of a Verilog Program A Verilog program is structured as a set of modules, which may represent anything from a collection.

VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.

Electrical Engineering Engineering the Future Digital Circuits Fundamentals Hands-on Full-Adder Simulation (afternoon)

ECEN 248 Lab 3: Study and Implementation of Adders Dept. of Electrical and Computer Engineering.

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – Lab2 Adders & Multiplexers.

Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals.

ECE 3130 Digital Electronics and Design

ECE 3130 Digital Electronics and Design

Introduction to Verilog

Introduction to Verilog

Introduction to Verilog

Number Systems and Circuits for Addition

Hasibul Hasan Ankit Baingane Edward Hanson

FIGURE 1: SERIAL ADDER BLOCK DIAGRAM

Introduction to Verilog

Introduction to Verilog

The Verilog Hardware Description Language

XOR Function Logic Symbol  Description  Truth Table 

Introduction to Verilog

Test Fixture Template module testfixture ; // data type declaration

NTU DSD (Digital System Design) 2007

EEE2243 Digital System Design Chapter 1: Verilog HDL (Combinational) by Muhazam Mustapha, February 2012.

Presentation transcript:

Today’s Lab Start working with Xilinx [pronounced: Zy-links] ISE design suite Create new project Enter code Synthesize code Simulate code JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Half Adder AND to arrive at Carry XOR to arrive at Sum A B S C Inputs Outputs A B S C 1 JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Half Adder Verilog Code module half_adder (A, B, Sum, C_out); input A, B; output Sum, C_out; xor (Sum, A, B); and (C_out, A, B); endmodule JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Creating a New Project JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

New Project Options JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Create the Verilog file JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Synthesize Verilog File JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Schematic view JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

Simulation Waveforms JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012