1. LECTURE VII SECTION 4.12 PART 1 MODELS OF COMBINATIONAL CIRCUITS

2. Gate-level modeling Uses instantiations of predefined primitives and user defined primitives. Outputs of these primitives are assigned by the simulator to be one of four possible conditions: 1) 1 or HI 2) 0 or LOW 3) z or high impedance: As with a non-enabled tri- state buffer 4) x or unknown: As when certain inputs have not been forced HI or LOW and the simulator has no way of knowing what the output should be.

3. Some identifiers can have multiple bit widths, called vectors. For example: output [0:3] D represents an output identifier (D) with four different outputs (vectors) which are represented as D[0], D[1], D[2], & D[3]. The leftmost number within the brackets of the original statement is the MSB (most significant bit), in this case D[0].

4. An example of a vector can be seen in this module of a 2 to 4 line decoder:

6. Note that D, both in the Objects box and the Wave box cannot be fully seen until expanded by clicking on the "+" button to the left of the "D" identifier.

7. There are two types of approaches to writing Verilog code which involve multiple modules which instantiate each other in a hierarchical manner. The first is known as bottom-up which means that the building blocks for the main module are written first. The second is known as top-down in which the main module is written first followed by the building block modules which it will instantiate. It is important to note that one module CANNOT be written within another module, i.e. between the keywords module and endmodule. Remember, Verilog does NOT employ a downflow programming style so either approach works in all cases.

8. Show below is a Verilog project showing a 4- bit ripple carry adder using a bottom-up approach. As a reminder, shown here are the schematics for the half-adder and the full-adders needed to make the 4-bit adder:

10. Show below is the Verilog code for the 4-bit ripple carry adder.

11. Adding 0010 + 0010 and then 1111 + 1111