1. Test Fixture Template module testfixture ; // data type declaration
// instantiate modules under test
// Applying stimulus
// Display results
endmodule

2. Test Fixture - Data Type Declaration
module testfixture ;
// data type declaration
reg a, b, sel ; // the inputs of Device Under Test
// instantiate modules under test
// Applying stimulus
// Display results
endmodule

3. Test Fixture - Instantiate
module testfixture ;
// data type declaration
reg a, b, sel ; // the inputs of Device Under Test
// instantiate modules under test
mux2_1 u1 (out, a, b, sel) ;
// Applying stimulus
// Display results
endmodule

4. Test Fixture - Stimulus
module testfixture ;
// data type declaration
reg a, b, sel ; // the inputs of Device Under Test
// instantiate modules under test
mux2_1 u1 (out, a, b, sel) ;
// Applying stimulus using an initial block
initial
begin
a=0 ; b=1 ; sel=0 ;
#5 b=0 ;
#5 b=1 ; sel=1 ;
end
// Display results
endmodule

5. Display results //Display results initial begin
$display(" time out a b sel");
$monitor($time, " %b %b %b %b", out,a,b,sel) ;
end

6. Lab 1: Verilog for Combinational Ckts
Install Xilinx ISE
Two simple examples
2-to-1 multiplexor (structural)
3-to-8 decoder
Verilog simulation

7. Lab 1-1 7-segment decoder input [3:0] in; output a,b,c,d,e,f ;
active low
RTL description
always block
(in)
a test fixture
print out waveform

8. Lab 1-2 4-bit magnitude comparator input [3:0] a, b ;
input agb, alb, aeb ;
output agbo, albo, aebo ;
RTL description
check inputs with high priority first
quiz

9. The truth table