Virtual Memory on x86

Virtual Memory Refresher Problems with using raw memory: – Isolation Protect system and programs from other programs Two programs want to write to the same address – Programs need more memory than was available Solutions – Segmentation – Paging

Segmentation Divides memory into segments Can offer isolation between segments – Protects system and programs from external access – Raises hardware exception on invalid access: segmentation fault

Paging Disk can be used to extend memory beyond physical memory capacity Virtual Addresses fake addresses which translate to physical addresses Requires translation: page tables are needed Provides unique translations for each program Image from Wikipedia

Page Tables Provide translation from virtual to physical memory addresses Register points to base of current programs table Part of the virtual address is used to index the table, which has the following for each entry: – Various bits representing access and usage – Index of another table or physical memory pages

Page Fault What happens when a program attempts to access a virtual address when the corresponding physical page is not present in memory? – Trap and attempt to make the physical address available Find a free page Replace an old page with the new page What if the page isnt found? – Trap again Invalid page fault Code usually terminated

Memory on x86 Modern x86 supports 3 memory models: – Allows use of paging – supports 4KB and 4MB page sizes – Segmentation – Flat Model – direct mapping (no virtual memory) x86_64 – Did away with segmentation (mostly) – Extended the virtual memory space from 4GB (ignoring PAE) to 16EB (exa-bytes) – Added another level of page tables

Paging Specifics for x86 x86 has a 3 level paging hierarchy: – Page directory – the topmost table – Page table – the intermediate table (when using 4KB pages) – Pages – 4KB or 4MB contiguous blocks of memory x86_64 supports additional modes: – Long mode includes a 4 level hierarchy Supports additional physical memory space – Additional control bits – such as No Execute

4kb Paging on x86 Image from Wikipedia

Paging Registers CR0 controls various aspects, such as enabling or disabling paging, caching, write-through and more. CR2 contains the virtual address responsible for a page fault The upper 20 bits of the CR3 register become the Page Directory Base Register (PDBR), which stores the address of the first page directory entry.

x86 Page Directory Entries x86s top level table 4MB mode – 10 most significant bits for indexing pages – Next 10 bits reserved – Remaining 12 bits set permissions and functionality as well as marking accesses and dirtiness 4KB mode – 20 most significant bits for indexing the page table – Remaining 12 bits set permissions and functionality as well as marking accesses

x86 Page Table Entries Used only in x86s 4KB paging 20 most significant bits for indexing pages Remaining 12 bits set permissions and functionality as well as marking accesses and dirtiness

Page Faults on x86 Page faults will throw an interrupt Handled like all procedure calls, exceptions, and interrupts – Push relevant registers to stack, push error code – Load/clear relevant registers – Run handler

PAE Feature allowing x86 to handle up to 36-bit physical addresses – Allows for up to 64GB of virtual memory – Still only uses 32-bit virtual addresses, so individual processes can only use 4GB of memory Due to additional addresses in the page directory and page table, CR3 must point to a higher level table, which contains 4 page directory tables.

X86 Resources nces/IA32-ref-manual-vol-1.pdf nces/IA32-ref-manual-vol-2a.pdf nces/IA32-ref-manual-vol-2b.pdf nces/IA32-ref-manual-vol-3.pdf