1. Virtual Memory Main Memory Magnetic Disk Upper level Lower level

2. Objective Main memory acts as a “cache” for the magnetic disk memory can be shared between several programs (and users) allows programs access to much greater “memory” than would otherwise be possible transparent to programs

3. Unique Address Space Need common set of addresses applicable for an entire program this is called the program address space Usable only by this particular program and no others Common addressing mechanism for both items stored in main memory and items stored on disk.

4. Terminology Physical address - the address of an item in main memory Virtual address - the address of an item in the virtual address space of a program, that can be translated to a physical address. There are many more virtual addresses than physical addresses, so that not all virtual addresses can simultaneously refer to real addresses in main memory.

5. More terminology A page (cf. “block”) is a large contiguous sequence of virtual memory addresses. A page fault (“miss”) occurs when a virtual address is referenced that does not correspond to a physical address. virtual addresses physical addresses disk locations

6. Page Faults Page faults are extremely costly taking 100,000s of times longer than a direct memory access Therefore minimisation of the probability of a page fault is a vital goal in memory hierarchy design Whereas the cache miss rate is normally between 0.1% to 20% the page fault rate is between 0.00001% to 0.0001%.

7. Minimising Page Faults Use large page sizes (4MB to 64MB) Allow flexible placement of pages in main memory Use “smart” complex algorithms to place pages in memory Reduce the number of writes to disk.

8. Virtual Address Structure of a virtual memory address: page offsetvirtual page number page offsetphysical page number mapping k bits n bits m bits m < n Number of physical pages = 2 m Page size = 2 k bytes

9. Virtual to Physical Mapping A virtual page can be mapped to any physical page This is a fully associative mapping: Contrast this with direct mapping used between cache and main memory, where each memory address corresponds to one fixed address in the cache. Each program maintains a corresponding page table for this map.

10. Page Table Stored in Memory page offsetvirtual page number Virtual address: n bits k bits 1 page offsetphysical page number m (< n) bits Valid There is an entry for every virtual address. Page Table Register

11. Handling Page Faults Alongside the page table there is a data structure that records where pages are located on disk. On a page fault this is used to write the page from disk to main memory. If all pages in main memory are already used, then a “least recently used” strategy is adopted to decide which page in physical memory should be dumped to make room for the new one.

12. Multiple Processes The state of a program (program A) is completely determined by its state table, the PC and the registers. Another program (B) can use the CPU provided that the state of the current program is saved. Program A can be reactivated when the OS reloads A’s state, and continues execution.

13. Protecting Address Spaces It is vital that the address spaces of different programs be kept completely separate. Only the OS should have the right to access any program’s address space. A program must not change its own page table. The hardware must support “user processes” and “executive processes” Only the latter have freedom to change page tables.

14. Behaviour of Memory Hierachies Compulsory Misses: first access to the page (block) results in a fault (miss). so increase page (block) size Capacity misses: memory (cache) cannot contain all virtual addresses (main memory). so increase size of memory (cache) Collision misses: direct mapping causes several pages (blocks) to be mapped to one physical page (cache index). so use fully associative mapping.

15. The Gap Processor speed doubles every two years. Memory density increases by fourfold every three years. Speed of access to memory (DRAM) increases only linearly. Multi-level caching systems help to solve this problem.