IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved A System-on-Chip Implementation of the IEEE a MAC Layer Goran Panić, Daniel Dietterle Zoran Stamenković, Klaus Tittelbach-Helmrich

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Overview Introduction Protocol Implementation Hardware/Software Partitioning System Architecture Components Description Synthesis Results Estimated Area & Power Layout Results Final Design Results Summary 2

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Introduction Functionality of the MAC described in the IEEE a standard Wireless market Atheros, Intersil, Cisco, TI, … Target: baseband, MAC and radio transcieving part integrated on a single chip IHP MAC - designed as a complete solution on chip Easy integration with the baseband 3

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Design flow overview Protocol description Performance investigation Hw Acc design Architecture description System implementation SDL model Simulations & Measurements VHDL model Logic and Layout Synthesis Abstract and HDL level Translation to C model Hw/Sw partitioning System consideration Data preparation 4

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Protocol Implementation SDL Model Abstract protocol model Generation of C model Performance estimation in order to perform Hw/Sw partitioning 5

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Hardware Accelerator CRC Bus_Interface Control PHY_Interface Tx CRC RC4 CRC Channel_State TimersMIB Rx Processor bus On-chip RAMBaseband processor executes timing critical MAC functions Timers, CRC, RC4, address filter reduction of power consumption interface between baseband and CPU completely modeled in VHDL synthesized and simulated for 80MHz 5x512B single-port memory 2x256B dual-port memory soft resetable 6

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved System Architecture MIPS 4KEp Core Peripheral Bus Controller EC-to-X Bus Controller I 2 C Hw Acc UART 0 SRAMFLASH Serial 0 Serial 1 I 2 C EPP GPIO EJTAG UART 1 GPIO complete rtl description in VHDL/Verilog verification environment and synthesis scripts EC X#0 X#1 7

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved System Architecture MIPS 4KEp Core Peripheral Bus Controller EC-to-X Bus Controller I 2 C Hw Acc UART 0 Async RAMAsync ROM Serial 0 Serial 1 I 2 C EPP GPIO EJTAG UART 1 GPIO complete rtl description in VHDL/Verilog verification environment and synthesis scripts EC X#0 X#1 Test program Test Environment Components verification models 8

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Synthesis Results Design name Estimated area (%) Estimated power (%) MIPS core I 2 C bus controller UART x 23.5 EC-to-X bus controller Peripheral bus controller Accelerator core Single-port RAM 512B x Dual-port RAM 256B x GPIO Glue logic Chip

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved System Layout Facts Technology: IHP 0.25μm CMOS Area: ~ 30 mm 2 Number of gates: 420,000 NAND Number of pins: 140 sig + 16 pow Package: PQFP 208L 28*28*3.35P0.5 Peak Power: ~1W at 80 MHz, 2.5V Chip testing: Successful on Agilent

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Summary Presented design flow provides: Efficient and flexible modeling and implementation of a MAC protocol Low power High performance Easy integration to a baseband processing unit What can be done in the future: PCMCIA interface to TCP/IP layer (rev 1) Custom connection to the baseband (rev 1) Usage of high performance memory blocks (rev 1) Clock gating AMBA bus 11