NS9750 - Training Hardware

Serial Controller - UART

UART Overview 4 Serial Controller Channels (A,B,C,D) External GPIO connections via TXD, RXD, RTS, CTS, DTR, DSR, DCD, RI

UART Hardware Based upon NS7520 Serial Controller design with minor enhancements and bug fixes. Improved data capture and status reporting for Receive Buffer Closed conditions, for example. Bit-Rate generation from internal or external clocking source, supporting baud rates from 75 to 1,843,200 (x8 mode only) Data support via DMA or BBus Interrupt

UART Hardware Four 8-bit Character Match registers SW/HW Initiated XON/XOFF based on Character Match for Flow Control Flow Control Force Register to disable transmit state machine to transmit specified Character while TX_IDLE Error detection: FIFO overrun, Break, Parity or Frame Errors

UART Configuration Initialize per-channel Bit Rate Register to Enable EBIT Set TMODE = 1 and TCDR=RCDR (x8, x16, or x32) for asynchronous operation Set ClkMux to select the oscillator as the source Set N-value for desired Baud Rate (refer to Hardware Ref. Manual) Initialize Character Gap or Buffer Gap Timers

UART Configuration Initialize Control Register A for Channel Enable, Word Size, Stop Bits, Parity Enable, Break, RTS, DTR, Rx/Tx Interrupt or DMA Enables Initialize Control Register B for UART Mode, Char. Match, Enable Character or Buffer Gap Timers, RTS Flow Control Initialize BBus Utility GPIO Config registers to enable desired UART interface pins

Serial Controller SPI

SPI Overview 4 Serial Controller Channels (A,B,C,D) External GPIO connections via TXD, RXD, SPI Enable, SPI Clk

SPI Hardware Based upon NS7520 Serial Controller design with minor enhancements and bug fixes. All four SPI Clocking modes are functional as opposed to only Clk0 and Clk1 in the NS7520, for example Bit-Rate generation from internal or external clocking source Data support via DMA or BBus Interrupt

SPI Hardware Four 8-bit Character Match registers Flow Control Force Register to disable transmit state machine to transmit specified Character while TX_IDLE Error detection: FIFO overrun SPI-EEPROM Boot from SDRAM following powerup (Serial ChanA only.)

SPI Master Configuration Initialize per-channel Bit Rate Register to Enable EBIT Set TMODE=1 and TCDR=RCDR=0 for synchronous (x1) operation Enable TXEXT to drive transmit clock via GPIOs Set ClkMux to select BCLK as the source Set SPCPOL, RXCINV, TXCINV to select the desired SPI Clock Mode (refer to Hardware Ref. Manual) Set N-value for desired Bit Rate (refer to Hardware Ref. Manual)

SPI Master Configuration Initialize Control Register A for Channel Enable, Word Size, Rx/Tx Interrupt or DMA Enables Initialize Control Register B for SPI Master Mode, SPI Enable Polarity, Bit Order, Character Match, and Character or Buffer Gap Timers Enables Initialize Character Gap or Buffer Gap Timers Initialize BBus Utility GPIO Config registers to enable desired SPI Master interface pins