1. RX Serial Peripheral Interface (RSPI)
Hello and welcome to this Renesas Interactive module that covers the RX Serial Peripheral Interface.
3/2/2011
Rev. 1.00
© 2011 Renesas Electronics America Inc. All rights reserved.
00000-A

2. Agenda
This module contains a description of specific features of the RX Serial Peripheral Interface (RSPI).
For basic SPI technology and terms refer to SPI Overview Module.
For overview of RSPI features for a specific group refer to RX Technical Marketing Overview Module. This module describes number of channels, supported modes, and other specific items.
Contained in this Module
Block Diagram
Supported Modes
Interrupts
Error Detection & Handling
Command Registers
Writing and reading buffers
Setting the bit rate
Usage Notes
This module covers specific features of the Serial Peripheral Interface, or RSPI, found on RX MCUs. If you need basic information on SPI please refer to the SPI Overview Module. If you are looking for information that applies to a specific RX group please refer to that group's Technical Marketing Overview Module.
In this module we will cover
the RSPI’s block diagram
the modes supported, interrupts available
what errors are detected and how to handle them
command registers and how to sequence them together
how to read and write the transmit and receive buffers
setting the bit rate
and some helpful usage notes.
© 2011 Renesas Electronics America Inc. All rights reserved.

3. Block Diagram
This figure shows a block diagram of a typical RSPI channel on a RX MCU. A RX MCU might have multiple RSPI channels.
Starting at the top right we see that the RSPI sits on the peripheral bus and that is uses the peripheral clock for baud rate generation. You will notice that the baud rate generator feeds the clock internally to the transmission reception controller as well as out to the RSPCKn, or SPI clock, pin. Notice that the RSPCKn has arrows on both ends. This is because it can send out the clock in SPI master mode and also accepts an incoming clock when the RSPI peripheral is in slave mode.
To the left of the baud rate generator is the transmission reception controller that has all of the peripherals registers.
Coming out and to the right of the transmission reception controller you will see the interrupts that can be generated by the RSPI peripheral.
Coming out and to the left of the transmission reception controller you can see the slave select signals that can be controlled by the RSPI peripherals. The polarity of each slave select signal is controlled by bits in the RSPI slave select polarity register.
On the left side of the figure you will find the transmit and receive buffers which are read and written using the RSPI Data Register.
Below this you have the parity circuit for error detection and the RSPI's shift register which can send bits out MSB or LSB first.
Under the shift register you will find the loopback circuitry which can be used along with the self-diagnosis function to check for errors in the parity circuit and error detecting unit.
Finally, you can see the Master-Out-Slave-In, also called MOSI, and Master-In-Slave-Out, also called MISO, pins used for transmission and reception. All of the RSPI output pins as a whole can be configured as CMOS or Open-Drain outputs using the RSPI output pin mode bit in the RSPI pin control register.
© 2011 Renesas Electronics America Inc. All rights reserved.

4. SPI Modes – Single-Master
We will now cover the modes supported by the RSPI peripheral. We will start off with Single-Master mode where the RX MCU is the only master on the SPI bus. In this mode the SPI clock, MOSI, and MISO pins are shared by all devices with the RX supplying the clock.
Each slave device has its own slave select line which is controlled by the RSPI peripheral. These slave select lines are how the RX master device selects which device should receive the data it is about to send. Only one slave select will be active at a time.
© 2011 Renesas Electronics America Inc. All rights reserved.

5. SPI Modes – Multi-Master
The RX also supports multi-master SPI mode. In this mode the RX uses slave select 0 and a general I/O pin to choose which master device has control of the bus. For an example, let's look at this master device. If the RX wants to take control of the bus then it would assert ACTIVE on its general I/O pin, Port Y in this example. At this point the others masters on the bus will recognize that another master has requested control of the bus and will make their pins high-impedance.
Conversely, if another master device wanted control then it would assert ACTIVE onto the slave select 0 line of the RX. At this point the RX will recognize that another master device has requested bus use and will pull off the bus. The RX will also trigger a mode fault error at this point.
© 2011 Renesas Electronics America Inc. All rights reserved.

6. SPI Modes - Slave
The RX also supports SPI slave mode. In this mode the RSPCK pin is set as an input and the RX accepts the clock from the master device, the MOSI pin becomes an input, the MISO pin becomes an output, and the slave select 0 pin becomes an input where the master can enable the peripheral.
© 2011 Renesas Electronics America Inc. All rights reserved.

7. Clock Synchronous Modes
The RX’s RSPI peripheral also supports master and slave clock synchronous modes. These modes work the same way as the SPI modes except the slave select lines are not used and the mode fault error is not triggered if there are multiple master devices. If the user needs a slave select line in this mode then they should use a general I/O pin and control the signal themselves.
© 2011 Renesas Electronics America Inc. All rights reserved.

8. RSPI Interrupts & Errors
Receive Buffer Full
Transmit Buffer Empty
Error
Idle
RSPI Control Register (SPCR)
RSPI Control Register 2 (SPCR2)
The RSPI peripheral has 4 interrupt sources.
The first is the receive buffer full interrupt. This interrupt triggers when data has been received and the buffer needs to be read. When taking this interrupt the user should immediately read the data from the buffer so that an overrun error does not occur.
There is also a transmit buffer empty interrupt. This interrupt triggers when the transmit buffer has successfully transmitted all of its previous data and is ready for new data. When taking this interrupt the user can fill the transmit buffer with the next data that needs to be sent.
The error interrupt triggers when any of the 3 RSPI errors occur. These errors are discussed on the next slide.
The last RSPI interrupt is the idle interrupt. This interrupt will fire whenever the RSPI peripheral is in the idle state.
When enabling the interrupts it should be noted that the enable bits for the receive buffer full, transmit buffer empty, and error interrupts are located in the RSPI control register while the enable bit for the RSPI idle interrupt will be found in the RSPI control register 2.
© 2011 Renesas Electronics America Inc. All rights reserved.

9. Errors & Error Handling
Overrun
Clear OVRF bit
Read data
Reinitialize if needed
Parity
Clear PERF bit
Mode Fault
Clear MODF bit
Set SPE bit
Reinitialize Flowchart
There are 3 errors that can be detected with the RSPI peripheral. When an error occurs it sets the appropriate flag in the RSPI status register. The user can also check which command register was being used when the error occurred by reading the RSPI error command bits in the RSPI sequence status register.
The first error is an overrun error. This error occurs when a serial transfer finishes and the previous data in the receive buffer has not yet been read. When this occurs the previous data is kept, the new data is discarded, and an overrun error is triggered. To clear this error the user should first clear the OVRF bit in the RSPI status register, then read the data from the receive buffer so that it is empty and will not overrun on the next data, and then reinitialize the RSPI's internal sequencer if needed. The flowchart on the right shows that a re-initialization is needed if the transmit buffer is not empty. To re-initialize the RSPI's internal sequencer the RSPI function enable bit in the RSPI control register should be set to 0 and then set to 1 to re-enable RSPI functionality.
The next error is a parity error. This error occurs when an incorrect parity bit is received when performing serial transfers. In order for this error to occur the parity function of the RSPI peripheral must be enabled. Handling this error is very similar to the handling the overrun error. The user should first clear the PERF bit in the RSPI status register and then reinitialize the RSPI's internal sequencer if necessary. Data does not need to be read from the receive buffer in this case since the data is corrupt.
The last error is a mode fault error. This error can occur when performing SPI operations in multi-master or slave mode. In multi-master mode this error is triggered when the slave select 0 signal is asserted while the peripheral is idle or transferring data. In slave mode the mode fault error is triggered when the slave select 0 signal is negated during a serial transfer and before it has finished. In either mode, when the error is detected the RSPI function enable bit is cleared to 0 which disables the RSPI peripheral. To handle this error the user should start by clearing the MODF bit in the RSPI status register.
Since a mode fault error disables the RSPI peripheral by clearing the SPE bit there is no need to check the transmit buffer status. Because of this the user will always need to re-enable the RSPI peripheral when this error is detected by setting the SPE bit in the RSPI control register to 1.
© 2011 Renesas Electronics America Inc. All rights reserved.

10. RSPI Command Registers
Control separate transfer formats
Phase
Polarity
Bit rate division
Slave select
Data length
LSB/MSB
Delays
Each RSPI channel has 8 command registers. Command registers are used for controlling separate transfer formats. When transmitting data the RSPI peripheral will always be using one of the command registers. Some of the settings that the command registers control are:
The phase of the SPI clock
The Polarity of the SPI clock
What if any divisor should be used on the base bit rate
Which slave select signal to assert
The number of bits to be transmitted. There are options to transmit between 8 and 32 bits per command.
Whether to transmit the data least-significant or most-significant bit first.<
And any needed delays which will be covered later.
What this gives to the user is flexibility. For instance the user could have Command register 0 set up to communicate with a SPI flash using one set of settings, like 8 bit data length, MSB first, slave select 0, and using the base bit rate. And then command register 1 setup with a completely different configuration with different phase and polarity, LSB first, 32 bits per transfer, and slave select 1.
At this point the user still has 6 more command registers to use which lets them easily interface to different devices.
© 2011 Renesas Electronics America Inc. All rights reserved.

11. RSPI Sequence Control Register
Command Sequence
RSPI Sequence Control Register
SPSLN = 0
0 >> 0 >> …
SPSLN = 1
0 >> 1 >> 0 >> …
SPSLN = 2
0 >> 1 >> 2 >> 0 >> 1 >> … …
SPSLN = 7
0 >> 1 >> 2 >> 3 >> 4 >> 5 >> 6 >> 7 >> 0 >> …
How many commands are used is controlled by the RSPI sequence control register.
The SPSLN bits in this register control the sequence length used by the RSPI peripheral. The first command to be used is always command 0, and commands used after that are sequential. Let’s look at some example settings. If the SPSLN bits are set to 0 then only command 0 will be used.
If the SPSLN bits are set to 1 then commands 0 and 1 will both be used. The way it works is that command 0 is used for a transfer and then the RSPI peripheral switches to command 1. After command 1 is used for a transfer the RSPI goes back to command 0 again.
As the value of SPSLN goes up, so does the number of commands used. The maximum value is 7 which would use all 8 command registers. The user can tell which command is currently being used by reading the RSPI command pointer in the RSPI sequence status register.
© 2011 Renesas Electronics America Inc. All rights reserved.

12. RSPI Frames & RSPI Data Register
Each command has Frame of between 8 and 32 bits
Command 0 – 8 bit frame
Command 1 – 32 bit frame
Command 2 – 16 bit frame
Write frames to RSPI Data Register (SPDR)
8 bits
8 bits
8 bits
Each command has a transfer bit length of between 8 and 32 bits. Whatever length is chosen becomes the frame size for that command.
So command 0 could be 8 bits,
Command 1 32 bits,
Command 2 16 bits, and so on.
Frames are written one at a time to the RSPI data register.
© 2011 Renesas Electronics America Inc. All rights reserved.

13. RSPI Data Register (SPDR)
32-bit buffer
Holds data for transmission and reception
Mapped to transmit (SPTX) and receive (SPRX) buffers
Accessed using word (16-bit) or longword (32-bit)
Can write up to four frames
The RSPI data register is a 32-bit buffer that holds data for transmission and reception. The RSPI has separate transmit and receive buffers, SPTX and SPRX respectively, that are mapped to the RSPI data register.
The data register should be read from or written to using either word, 16-bit, or longword, 32-bit, accesses. Which type of access should be used is determined by the SPLW bit in the RSPI Data Control Register. If the data register is set for 16-bit accesses then the maximum frame size that can be chosen by a command is 16 bits. If the data register is set for 32-bit accesses then any frame size can be chosen.
Up to four frames can be written to the data register. If 16-bit access is chosen this gives the user a maximum buffer size of 64 bits; and 128 bits with 32-bit accesses.
If the user tries to write the data register while the transmit buffer is still transmitting then the latest write will be ignored. If the user fails to read the previous data from the data register before the next serial transfer ends then an overrun error is detected and the new data is not stored.
© 2011 Renesas Electronics America Inc. All rights reserved.

14. RSPI Data Control Register
Control of which SSL pins are used
16 or 32 bit access to SPDR
Number of frames
The RSPI data control register controls several important features of the RSPI peripheral.
These include:
Selecting which slave select pins are used and which are reserved for general I/O use.
Selecting whether the RSPI data register should be read or written with 16 or 32 bit accesses.
The RSPI data control register also has the SPFC bits which allow the user to control how many frames are stored in the RSPI data register before a receive buffer full interrupt occurs or before the transmit buffer is actually transmitted. Let’s look at some examples using this table. Note that these are some example configurations and the user is not limited to only these options. The SPSLN column is from the RSPI sequence control register that we reviewed earlier and controls how many commands are used.
In this first example only 1 command is used which can be seen by the 0 bits in the SPSLN column and only 1 frame is needed for transmission or reception which is controlled by the 0 in the SPFC column.
On the next line notice that only the SPFC bits have changed. Now 2 frames are required. To review, in the first example, any time the RSPI data register is written the data would immediately be transmitted since only one frame was required. In this current example the user would need to write to the RSPI data register twice before the data is actually transmitted.
The next example we will look at uses two commands. Since we have two commands we can either transfer after 2 frames or 4 frames. As mentioned earlier the RSPI data register can hold up to four frames so once the number of commands used goes above 4, not all commands can be executed in one round of transmission.
For example, look at the last entry in the table. This entry uses all 8 commands. In this example the SPFC bits are 0 which means only 1 frame is transferred at time, but the user could change this to 3 which would transfer 4 frames a time. If that were the case, then commands 0 through 3 would transfer after the first four writes to the data register had been performed. After the second 4 writes had been performed commands 4 through 7 would be used. After that the commands would loop back to command 0. The user can also choose odd values for SPFC. Using this same example, if the SPFC bits had been 2 then 3 commands would be transmitted at once. The first set would be commands 0 through 2, the 2nd set would be commands 3 through 5, and the 3rd set would commands 6, 7, and 0 since it would loop back. The user can check which command is currently being used anytime by reading the RSPI command pointer bits in the RSPI sequence status register.
© 2011 Renesas Electronics America Inc. All rights reserved.

15. Set SSLKP bit in command register to 1
Burst Transfers
Set SSLKP bit in command register to 1
By default the RSPI will assert and then negate the slave select signal with each command that it transmits. By using the SSL Signal Level Keeping bit in the RSPI command registers the user can enable burst transfers where multiple commands are transmitted without the slave select changing between commands.
An example of this functionality is shown here. In this example there are multiple steps each one denoted by parentheses with a number in the middle. The first three steps highlighted here show the first command.
This second box shows the second command. The step we are interested in for this slide is step 4. This is after the first command has completed and is where the RSPI peripheral would usually negate the slave select signal to prepare for the next command. Since the first command’s SSLKP bit is set to 1 in this example the RSPI peripheral will keep the SSL signal from the end of the last transfer until the beginning of the next access.
Since the next command uses the same slave select polarity as the last command the slave select signal is never inverted and burst transfer is performed. The user could also setup more than 2 commands for a burst transfer. If 4 commands were used and the first 3 had their SSLKP bits set to 1 and they all used the same slave select polarity then the slave select signal would remain asserted until after the fourth command finished.
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16. Slave Select Negation Delay (t2) Next-Access Delay (t3)
Controllable Delays
Clock Delay (t1)
Slave Select Negation Delay (t2)
Next-Access Delay (t3)
There are 3 controllable delays that can be set for the RSPI peripheral. Each command register has bits to select which if any of the delays it wants to use. The delays are set peripheral wide, so if multiple commands enable the same delay they will all have the same delay period. This means that if the user is using multiple slave devices, the delays will need to be set for the device with the longest delay requirements.
Let’s go through and look at each delay. This figure shows an example serial transfer with the slave select signals, MISO and MOSI signals, sampling time, and SPI clock shown.
The first delay is the clock delay and it is represented in the figure as time span ‘t1’. The clock delay is the period between when the slave select signal is asserted and when the SPI clock starts oscillating. The shortest period that can be chosen is 1 SPI clock cycle and the maximum is 8 SPI clocks cycles.
The second delay is shown in the figure as ‘t2’ and it is the Slave Select Negation Delay. This delay is the period between the last transition of the SPI clock and when the slave select signal is negated. This delay also has a minimum period of 1 SPI clock cycle and a maximum of 8 cycles.
The third delay is the Next-Access Delay and is represented as t3. The Next-Access Delay is the period between the termination of one serial transfer and the start of the next. The shortest delay that can be chosen is the addition of 1 SPI clock cycle and 2 PCLK cycles. The longest delay is the addition of 8 SPI clock cycles and 2 PCLK cycles.
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17. Bit Rate = PCLK (Hz) 2 x (n + 1) x 2N Setting the Bit Rate
n = RSPI Bit Rate Register
N = Bit Rate Division Setting in Command Register
Setting the bit rate of the RSPI peripheral is a function of 3 variables as shown here:
The first variable is PCLK, the peripheral clock speed. The second variable is the value in the RSPI Bit Rate Register and is denoted by the lowercase letter 'n'. This is an 8-bit register and therefore can represent numbers from 0 to The third variable is the Bit Rate Division Setting for the current command being used which is represented in this equation
With the capital letter 'N'. This value is selected by the BRDV bits in each command register. The BRDV is 2 bits wide so it can hold a value between 0 and 3. What we will refer to as the base bit rate is the bit rate when the command register sets capital 'N' to 0 which means there is no division. Therefore, looking at the equation we see that this means the value of the BRDV bits allows each command to use the base bit rate, or the base bit rate divided by 2, 4, or 8.
The following table shows some example bit rates where the different parameters are varied. Notice the first line where both little 'n' and capital 'N' are 0. This is the fastest bit rate which can be set which is half the peripheral clock. Using the maximum value of SPBR and BRDV the PCLK can be divided by 4096.
© 2011 Renesas Electronics America Inc. All rights reserved.

18. Loopback Mode & Self-Diagnosis
The RSPI peripheral has a feature called Loopback Mode where when a serial transfer occurs the transmitted data also becomes the received data. This does not affect data being output. Loopback mode can be enabled in the RSPI Pin Control Register. Using loopback mode the user can enable Parity Self-Testing in the RSPI control register 2 and perform a self-diagnosis of the RSPI’s error detecting unit and parity circuit. Refer to your RX group’s hardware manual to review the steps needed to perform this diagnosis.
© 2011 Renesas Electronics America Inc. All rights reserved.

19. Parity function in master mode
Usage Notes
Enable each module
Parity function in master mode
Transfer bit length
MSB/LSB
On this slide we will cover some usage notes for the RSPI peripheral.
First, the user should always remember to bring each channel of RSPI that they are using out of the module stop state. This is done by clearing the bit in the module stop control registers that corresponds to the RSPI channel you are using. Please refer to the Low Power Consumption section of your RX group’s hardware manual to see which bits should be cleared. If this bit is not cleared then the RSPI peripheral will be disabled and its registers will not writable.
The second note has to do with using the parity function. When using the parity function in master mode all command registers must have the same values for the transfer bit length, and the endianess chosen.
© 2011 Renesas Electronics America Inc. All rights reserved.

20. Summary Block Diagram Supported Modes Interrupts
Errors & Error Handling
Command Registers
RSPI Data Register and Buffers
Burst Transfers
Controllable Delays
Bit Rate
Loopback Mode and Self-Diagnosis
Usage Notes
Thanks for Viewing!
In summary, in this module we covered:
the block diagram of the RX's RSPI peripheral,
The different modes supported,
What interrupts were available,
What errors are detected and how to handle them,
Command registers and how to use them together
The RSPI data register and how it works with the transmit and receive buffers,
How to enable burst transfers,
What delays can be set for serial transfers,
How to set the bit rate and control it within command registers,
Loopback mode and using it to self-diagnose the parity and error detecting units
And usage notes to be aware of when using the RSPI peripheral.
We would like to thank for viewing this module. You may consider viewing the technical marketing overview module for more information on RX MCUs.
© 2011 Renesas Electronics America Inc. All rights reserved.

21. RX-RSPI Quiz

22. © 2011 Renesas Electronics America Inc. All rights reserved.
Thank You
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© 2011 Renesas Electronics America Inc. All rights reserved.