ECE2030 Introduction to Computer Engineering Lecture 3: Switches and CMOS Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

Basic Switch A path exists when the Switch Control is closed If (Open) OUTPUT = unknown ; Switch is open (OFF) Else OUTPUT = INPUT ; Switch is closed (ON) Switch Control INPUT OUTPUT

The Analogy of A Transistor INPUT OUTPUT Switch Control (Gate) Cross Section An N-Channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET)

Transistor Characteristics Cut-off Region Vgs – Vt  0 No current (Ids) between drain and source Linear (or Ohmic) Region 0 < Vds < Vgs – Vt Ids is a function of Vgs and Vds Ids = β*[(Vgs-Vt)*Vds – Vds*Vds/2] Saturation Region 0 < Vgs – Vt < Vds Ids is independent of Vds Ids = (β/2)*(Vgs-Vt)2 β = process factor * (W/L) Vt : Threshold voltage, a function of materials, doping, insulator thickness, etc. Gate Drain Source Vds Ids Vgs N-type MOS Transistor

Transistor Characteristics

Switches in Series INPUT Truth Table S1 S1 S2 PATH? OFF ON S2 OUTPUT

Switches in Series S1 S2 PATH? OFF NO ON YES INPUT Truth Table (OFF/ON=0/1) S1 S1 S2 PATH? OFF NO ON YES S2 OUTPUT What Function ??

Switches in Series S1 S2 PATH? INPUT Truth Table (OFF/ON=0/1) S1 S2 S2 OUTPUT Function = ??

Switches in Series S1 S2 PATH? 1 INPUT Truth Table (OFF/ON=0/1) S1 S2 1 S2 OUTPUT Function = ??

Switches in Series S1 S2 PATH? 1 INPUT Truth Table (OFF/ON=0/1) S1 S2 1 S2 OUTPUT Function = ??

Switches in Series S1 S2 PATH? 1 INPUT Truth Table (OFF/ON=0/1) S1 S2 1 S2 OUTPUT Function = Logic AND

Switches in Parallel S1 S2 PATH? OFF NO ON YES INPUT Truth Table S1 S2 OUTPUT

Switches in Parallel S1 S2 PATH? INPUT Truth Table S1 S2 OUTPUT S1 S2 OUTPUT Function =??

Switches in Parallel S1 S2 PATH? 1 INPUT Truth Table S1 S2 OUTPUT 1 S1 S2 OUTPUT Function =??

Switches in Parallel S1 S2 PATH? 1 INPUT Truth Table S1 S2 OUTPUT 1 S1 S2 OUTPUT Function =??

Switches in Parallel S1 S2 PATH? 1 INPUT Truth Table S1 S2 OUTPUT 1 S1 S2 OUTPUT Function = Logic OR

CMOS Transistor Complementary MOS pMOS nMOS P-channel MOS (pMOS) N-channel MOS (nMOS) pMOS P-type source and drain diffusions N substrate Mobility by holes nMOS N-type source and drain diffusions P substrate Mobility by electrons Gate Source Drain pMOS Gate Drain Source nMOS

Pass Transistor using NMOS Assume capacitor (CL) is initially discharged Gate=1, Vin=1 CL begins to conduct and charges toward 1 (Vdd) and stops at (Vdd-Vt) Signal is degraded Gate=Vdd Vgs Vin=Vdd Vout I Load Capacitor Ground Gate=1, Vin=0 CL begins to discharge toward 0 Gate=Vdd Vin=0 Vout=Vdd Ground Load Capacitor Vgs I

Transmission Degradation using Pass Transistor Vdd (1) Vdd - Vt Vdd Vdd - 2Vt Vdd Vdd Vdd Vout = Vdd- N*Vt Still 1??

CMOS Signal Transfer Property Gate Source Drain Gate Path Closed 1 Open Transmits 1 well Transmits 0 poorly Transmits 0 well Transmits 1 poorly pMOS Gate Drain Source Gate Path Open 1 Closed nMOS

CMOS Transmission Gate Transmit signal from INPUT to OUTPUT when Gate is closed Gate (complementary of Gate) Gate pMOS nMOS OUTPUT OFF Z 1 ON INPUT Source Drain INPUT OUTPUT Z : High-Impedance State, consider the terminal is “floating” Gate

High Impedance When a path exists When no path Impedance is low to allow ample flow of current When no path Impedance is high allowing almost no current flow between two terminals Gate=1 << 10K Source Drain Closed Gate=0 >> 100M Source Drain Open

Transmission Gates Transmit Logic 0 Gate = 1 1 Gate = 0 Gate = 1

Transmission Gate Symbol INPUT OUTPUT  INPUT OUTPUT Gate Gate