Ruggedized Camera Encoder

Agenda Team Introduction Project Description Initial Requirements System Architecture Electrical Design Software Design Mechanical Design Future Work Lessons Learned P14571 - Ruggedized Camera Encoder

Team Introduction Matthew Hornyak– Mechanical Engineer Alonzo Moreno – Mechanical Engineer Jordan O’Connor – Electrical Engineer Lennard Streat – Computer Engineer Kyle Jason – Electrical Engineer (PM) P14571 - Ruggedized Camera Encoder

Project Description A Ruggedized Camera Encoder (RCE) is a compact and robust system that analyzes a stream of image data in real-time. This system will eliminate the need for post processing. Real-world applications are desired by the customer such as, police vehicles or military uses. Deliver a working prototype that will acquire HD 1080p 30fps image data.

Initial Requirements General Customer Requirements Pull 1080p 30fps Video from CoaXPress Camera Portable Ruggedized/Waterproof Interface with D3 Design Core I/O (HDMI, SSDs, SD card, USB, etc.) Multiple Cameras Real-time Video Analytics (Object recognition, Event triggering) General Engineering Requirements High Speed Transceivers SoC FPGA I/O Ports and Protocols Performance Constraints Environmental Constraints Misc. Constraints P14571 - Ruggedized Camera Encoder

System Architecture A Ruggedized Camera Encoder (RCE) is a compact and robust system that analyzes a stream of image data in real-time. Typically, video analytics are completed using post processing techniques on a unit that is separate from the camera stream. This system will eliminate the need for post processing which cuts down on turnaround time and the need for a secondary system. Currently, the encoder used is more ideal for low-end applications and not real-world applications desired by the customer such as, police vehicles or military uses. The encoder should also be easily able to interface with other devices and not just cameras. The goal of this project is to deliver a working prototype that will have a small enclosure (tabletop) with two tethered camera inputs, acquiring HD 1080p 30fps image data. The system will be capable of processing the image data in real-time running different video analytics algorithms. It will be capable of streaming compressed image data over GigE to a standard video client for diagnostics through the D3 Design Core module. P14571 - Ruggedized Camera Encoder

Electrical Design: FPGA Cyclone V SoC Peripheral Part Selection Reference Design P14571 - Ruggedized Camera Encoder

Electrical Design: FPGA cont. DDR3 section of Schematics Design Complexity P14571 - Ruggedized Camera Encoder

Electrical Design: CoaXPress HDMI CXP Equalization – EqcoLogic ICs HSMC Interface – XCVRs & LVTTL ADC System – Power of CXP (PoCXP) Physical Layer – PCB Design, I/O & Power CoaXPress HSMC functional diagram. P14571 - Ruggedized Camera Encoder

CoaXPress: Equalization A high-level depiction of the CoaXPress protocol, from an interface perspective. P14571 - Ruggedized Camera Encoder

CoaXPress: HSMC Interface Three Major Signal Groups High-Speed Transceiver Data Lines (2x/channel) Low-Speed Uplink (1x/channel) PoCXP Power Control Signal (1x/channel) I2C Data & Clock Lines (PoCXP Sense) HDMI IP Signals P14571 - Ruggedized Camera Encoder

CoaXPress: PoCXP Subsystem PoCXP control circuit. This circuit is duplicated for each CXP input channel; 4 channels. The PoCXP sense signals are each connected to two 4-Channel ADS1015 Analog to Digital Converters. P14571 - Ruggedized Camera Encoder

CoaXPress Subsystem: Physical Design (Left) Power Tree. (Right) 3D View of CXP HSMC PCB design. P14571 - Ruggedized Camera Encoder

Software Design

Software: Continued Three Major Parts: Camera Interfacing (Transceiver) Decoding and Storage Display Video Stream (And Stored Data) Tools: Altera Quartus II, Qsys, Altera Embedded Design Suite Languages: Verilog (Qsys system and Blocks), C (SoC scripts) Software currently under development

Mechanical Design: IP67 IP First Digit (Ingress of Solid Objects) Second Digit (Ingress of Liquids) No protection ... 4 Protected against solid objects over 1.0mm e.g. wires. Protected against splash water from any direction. 5 Limited protection against dust ingress. (no harmful deposit) Protected against low pressure water jets from any direction. Limited ingress permitted. 6 Totally protected against dust ingress. Protected against high pressure water jets from any direction. Limited ingress permitted. 7 N/A Protected against short periods of immersion in water. 8 Protected against long, durable periods of immersion in water. 9K Protected against close-range high pressure, high temperature spray downs.

Mechanical Design: 1st Design

Mechanical Design: 2nd Design $550 in parts

Mechanical Design: Final Design CXP HSMC Heat Dissipation Tray Tray Access Panel HDD Tray $470 in parts

Mechanical Design: Heat Analysis

Future Work Mechanical: Fabrication of the Parts Arrange Final Placement of Internal Components Heat, Force, and IP67 Testing Electrical: Finish FPGA Board Schematics and PCB Finish CXP board PCB Integrate Both Boards into System Software: Complete Transceiver Testing Implement ARM Control of FPGA

Lessons Learned Avoid setting unrealistic goals (smaller steps in deliverables) Know when to move forward Working remotely is not ideal Rely less on customer for mission critical components Product design process System integration

Project Status and Questions Research complete Product design almost complete Design almost ready for implementation Questions?