Lecture 14 - Dynamic Memory 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory In chapter 7 of 2nd Edition of text. VLSI of DRAM How implemented Timing concerns Sample system 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory The memory cell The storage cell is simply a MOS capacitor The capacitor is “leaky” Cell needs to have its charge “restored” before it leaks away. Needs refreshed 9/20/6 Lecture 14 - Dynamic Memory

The storage transistor Why it leaks The storage transistor The input transistor Leakage is through reversed biased p-n junction 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory DRAM Memory system Low cost random access memory Usually large size memory Common sizes 256K x 1-bit, 512K x 1-bit, 1M x 1-bit, 1M x 4-bits Requires facility to “refresh” the memory Address pins are typically multiplexed Chips have a RAS* and CAS* input 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory DRAM memory Alpha particle susceptible Memories that detect and correct for errors SED – Single Error Detection – parity bit SEC-DED – Single Error Correction, Double Error Detection Requires an extra 5 bits per byte Keeps “codewords” seperated by 1 from “non-codewords” 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory DRAM System Note- chips often have separate data in and data out pins. 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory Timing 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory Timing Details 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory Read Cycle Timing 9/20/6 Lecture 14 - Dynamic Memory

W* Timing in a read cycle Needed for refresh 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory Write cycle timing RAS* & CAS* same in both read and write 9/20/6 Lecture 14 - Dynamic Memory

Detailed write cycle timing 9/20/6 Lecture 14 - Dynamic Memory

Generating signal timing 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory Refresh Readout of data is “destructive” to data Must be written back each time chip is read. When particular row of the memory array is accessed, all columns of that row are refreshed. Row must be refreshed every x seconds For the 514400 this is 16ms 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory Refresh methods RAS* only refresh CAS* before RAS* refreshing Avoids the need for a row-refresh address generator Special DRAM control logic called a DRAM controller 9/20/6 Lecture 14 - Dynamic Memory

Lecture 14 - Dynamic Memory Memory Subsystem 9/20/6 Lecture 14 - Dynamic Memory