1. Lecture No. 41
Memory

2. Recap Sync. Burst SRAM Burst Logic Circuitry DRAM Structure
Flow through SRAM
Pipelined SRAM
Burst Logic Circuitry
DRAM Structure
Writing to DRAM
Reading from DRAM
Refreshing DRAM
Address Multiplexing

3. DRAM Access DRAM Read Cycle (fig 1a) DRAM Write Cycle (fig 1b)
FAST Page Access Mode (fig 2)

4. DRAM Refresh Burst Refresh 1024 row refreshed in 8 ms
Distributed Refresh single row refreshed in 7.8 microsec
RAS only refresh
CAS before RAS refresh
DRAM Types
FAST Page Mode
Extended Data Output
Synchronous DRAM

5. ROMS ROM Types Cell implementation of a Mask ROM (fig3)
PROM
EPROM (UV EPROM & EEPROM)
Cell implementation of a Mask ROM (fig3)
General structure of ROM (fig4)
256 x 4 ROM implementation (fig5)
ROM applications (tab 1)
ROM Read cycle and access time (fig6)

6. Programmable ROMS PROM structure (fig 7) EPROM UV EPROM symbol (fig 8)
Programming UV EPROM
EEPROM

7. FLASH ROM FLASH Floating Gate cell implementation (fig 9)
Read/Write, non-volatile, high density, fast access time, cost effective
Floating Gate cell implementation (fig 9)
Programming Operation (fig 10)
Read Operation (fig 11)
Erase Operation (fig 12)
FLASH Structure (fig 13)
Memory Summary (tab 2)

8. Memory Expansion Memory Expansion Special Memory Types
Expanding Data Unit size (fig 14a)
Expanding Locations (fig 14b)
Expanding Data unit size and locations (fig 14c)
Special Memory Types
FIFO (fig 15)
LIFO (fig 16)