FPGA Project I: Up/Down Counter w/ Async Reset Slides Available at: www.pages.drexel.edu/~mjm46 Matthew Murach

Methodology You are to design a basic 4 bit (0 thru F) counter This design should change state every 50 million clock cycles The counter will go up depending on which position is set on the u/d switch The counter should go to 0 immediately if the reset push button is pressed.

Layout in FPGA Counter Output.vhd (Made in the Tutorial) Counter S(0:7) D(0) Counter Controller.vhd Counter Output.vhd (Made in the Tutorial) Reset D(1) p54 D(2) U/D SW D(3) p93 To Display Clk p88

Logic for Design Your design can implement the design using several techniques. You could use a two state (one up and one down w/ the ieee arith library to perform addition and subtraction). You would switch the states on a press of the u/d button. You can program 16 states for all the positions of the counter and change the state accordingly depending on the u/d value.

Global Reset Async reset can be done in the following fashion Example: Architecture Behav of counter is Begin Process(clk) if (reset = ‘1’) then -- Active High Reset disp := “0000”; else -- insert state table here (s0,s1, etc) end if; End process; End Behav;

Counter Synchronization Since the clock of the device is around 50 MHz, you need to slow down the system so that you can see the output on the 7 segment LED display. Use a variable to count 50 million cycles. When this variable reaches 50 million the counter changes up/down depending on the value of the switch.

Wrap Around Counter The program should wrap around to 0 if up is asserted and the display is F The program should wrap around to F if down is asserted and the display is 0

Grading This project is to be done in the lab and will be checked off on completion. This project should take around 1- 1 1/2 hours to complete No report will be collected for this assignment There is no deadline on this assignment.