VLSI Testing Lecture 12: Alternate Test Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal IIT Delhi, Aug 24, 2013, 11:00AM-12:00PM Copyright 2012, Agrawal Lecture 12: Alternate Test

Lecture 12: Alternate Test Contents Setting thresholds in model-based test Alternate test Summary References Copyright 2012, Agrawal Lecture 12: Alternate Test

Setting Thresholds in Model-Based Test In model-based test, component values are tested. Preset “thresholds” for component variation classify the device under test as good or faulty. How do we determine the “thresholds”? For example, Circuit is good if R1’ ≤ R1 ≤ R1’’ Copyright 2012, Agrawal Lecture 12: Alternate Test

An Operational Amplifier + _ Gain = V2/V1 = R2/R1 V1 V2 Copyright 2012, Agrawal Lecture 12: Alternate Test

Pessimism in Model-Based Test Slope = G Yield loss R2 Only good devices accepted R1 Copyright 2012, Agrawal Lecture 12: Alternate Test

Lecture 12: Alternate Test Reducing Yield Loss Slope = G Reduced yield loss R2 Faulty devices accepted R1 Copyright 2012, Agrawal Lecture 12: Alternate Test

Yield Loss and Defect Level Yield loss: Amount of yield reduction because some good devices fail non-functional tests. Defect level (DL): Fraction of faulty devices among those that pass non-functional tests. Example: 1,0000 devices are fabricated. 7,000 are good. True yield, y = 0.7. Test passes 6,900 good and 150 bad devices. Then, Yield loss = (7,000 – 6,900)/10,000 = 0.01 or 1% DL = 150/(6,900+150) = 0.02128 or 2.128% or 21,280 DPM (defective parts per million) Copyright 2012, Agrawal Lecture 12: Alternate Test

Yield Loss and Defect Level All fabricated devices Devices passing test Good devices Defect level Yield loss Copyright 2012, Agrawal Lecture 12: Alternate Test

Component Variation (Statistical) Uniform Gaussian Mean Mean Component (R or C) value Component (R or C) value Copyright 2012, Agrawal Lecture 12: Alternate Test

Monte Carlo Simulation Consider operational amplifier example: R1 and R2 are random variables with given (uniform or Gaussian) probability density functions with Mean = nominal value Standard deviation based on manufacturing data Generate large number of samples for R1 and R2 Simulate each sample using spice Determine gain for each sample For each set of tolerance limits on R1 and R2, determine yield loss and defect level. Copyright 2012, Agrawal Lecture 12: Alternate Test

Monte Carlo Simulation Data Slope = G R2 R1 Copyright 2012, Agrawal Lecture 12: Alternate Test

Lecture 12: Alternate Test Setting Test Limits Minimize yield loss Slope = G R2 Minimize defect level R1 Copyright 2012, Agrawal Lecture 12: Alternate Test

Lecture 12: Alternate Test Besides components (e.g., R1 and R2 for operational amplifier) easily measurable parameters used for testing. An example is the supply current IDD of the operational amplifier. A simple test is to measure IDD(0) for 0V input. Monte Carlo simulation is then used to set the limits on IDD(0). Large number of sample circuits with component variations are simulated to determine thresholds for IDD(0). Additional measurements can improve test. Copyright 2012, Agrawal Lecture 12: Alternate Test

Alternate Test: Setting Thresholds Minimize yield loss Within spec. gain Gain Minimize defect level Fail Pass Fail IDD(0) Copyright 2012, Agrawal Lecture 12: Alternate Test

Lecture 12: Alternate Test References P. N. Variyam, S. Cherubal and A. Chatterjee, “Prediction of Analog Performance Parameters Using Fast Transient Testing,” IEEE Trans. Computer-Aided Design, vol. 21, no. 3, pp. 349-361, March 2002. H.-G. Stratigopoulos and Y. Makris, “Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing,” IEEE Trans. Computer-Aided Design, vol. 27, no. 2, pp. 339-351, February 2008. Copyright 2012, Agrawal Lecture 12: Alternate Test